HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 262

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

4.2.2
4.2.3
Intel
Datasheet
262
®
5100 Memory Controller Hub Chipset
Legacy VGA Ranges (A 0000h–B FFFFh)
The 128 kB Video Graphics Adapter Memory range (A 0000h to B FFFFh) can be
mapped to the VGA device which may be on any PCI Express* or ESI port, or optionally
it can be mapped to main memory (it must be mapped to SMM space). Mapping of this
region is controlled by the VGA steering bits. At power-on, this space is mapped to the
ESI port.
Priority for VGA mapping is constant in that the MCH consistently decodes internally
mapped devices first. The MCH positively decodes internally mapped devices. This
region can be redirected by BIOS to point to any bus which has a VGA card. If the
VGAEN bit is set in one of the SC.BCTRL configuration registers associated with the PCI
Express* port, then transactions in this space are sent to that PCI Express* port.
The VGAEN bit can only be set in one and only one of the SC.BCTRL registers. If any
VGAEN bits are set, all the ISAEN bits must be set. If the VGAEN bit of a PCI Express*
port x in the Intel
zero, then ISAEN bits of all peer PCI Express* ports with valid I/O range (PEXCMD.IOAE
= 1, IOLIMIT >= IOBASE) in the MCH must be set by software. Otherwise, it is a
programming error due to the resulting routing conflict.
If the VGAEN bit of a PCI Express* port x in the MCH is set, and
BCTRL[x].VGA16bdecode is set to one, and if there is another PCI Express* port y (x
!= y) with valid I/O range including the lowest 4 kB I/O addresses (PEXCMD[y].IOAE =
1, IOLIMIT[y] >= IOBASE[y] = 0000h), BCTRL[y].ISAEN bit must be set to one by
software. Otherwise, it is a programming error.
This region is non-cacheable.
Compatible SMRAM Address Range (A 0000h–B FFFFh)
The legacy VGA range may also be used for mapping SMM space. The SMM range (128
kB) can overlay the VGA range in the A and B segments. If the SMM range overlaps an
enabled VGA range then the state of the SMMEM# signal determines where accesses to
the SMM Range are directed. SMMEM# is a special FSB message bit that uses
multiplexed address bit FSBxA[7]#. SMMEM# is valid during the second half of the FSB
request phase clock. (the clock in which FSBxADS# is driven asserted).
SMMEM# asserted directs the accesses to the memory and SMMEM# deasserted
directs the access to the PCI Express* bus where VGA has been mapped.
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at this address. Non-SMM-mode processor
accesses to this range are considered to be to the video buffer area as described above.
Graphics port and ESI originated cycles to enabled SMM space are not allowed and are
considered to be to the Video Buffer Area.
Monochrome Display Adapter (MDA) Range (B 0000h–B 7FFFh)
The Intel
Expansion Card BIOS Area (C 0000h–D FFFFh)
This 128-kB ISA Expansion Card BIOS covers segments C and D. This region is further
divided into eight, 16-kB segments. Each segment can be assigned one of four read/
write states: read only, write only, read/write, or disabled. Typically, these blocks are
mapped through the MCH and are subtractively decoded to ISA space. Memory that is
disabled is not remapped.
®
5100 MCH Chipset does not support this range.
®
5100 MCH Chipset is set and BCTRL[x].VGA16bdecode is set to
Intel
®
5100 MCH Chipset—System Address Map
Order Number: 318378-005US
July 2009