HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 60

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.10
2.10.1
2.10.1.1
Figure 5.
Intel
Datasheet
60
Note:
®
5100 Memory Controller Hub Chipset
Synchronized RESETI#
Synchronized RESETI# is the RESETI# signal synchronized with the necessary internal clock domain, the PLLs are the
internal PLLs locking to the BUSCLK signal and POC is Power-On Configuration, see
processor RESET#
PCI Express*
Power Rails
PWRGOOD
RESETI#
BUSCLK
Reset Requirements
Timing Diagrams
Power-Up
The power-up sequence is illustrated in
Power-Up
Events
PLL's
POC
ESI
Internal power detect
Non-DDR Analog
compensation
completed
T1
sampled
Straps
T7
T8
T10
T9
inactive
Figure 5, “Power-Up.”
Straps
downloaded
Fuses
Intel
T11
®
5100 MCH Chipset—Signal Description
T13
initialization
Section 1.1,
T12
Array Init
Done
Order Number: 318378-005US
“Terminology”.
ESI handshake started
T15
full operation
T14
0727061256
July 2009