HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 145

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
31:24
23:18
17:15
14:12
11:10
Bit
RWO
®
Attr
RO
RO
RO
RV
5100 MCH Chipset
7-2, 0
0
78h
{07h} endif
{02h} elsif
{03h} elsif
{04h} elsif
{05h} elsif
{06h} elsif
if (port 0)
{0h} elsif
Default
(port 2)
(port 3)
(port 4)
(port 5)
(port 6)
(port 7)
111
111
6h
01
PN: Port Number
This field indicates the PCI Express* port number for the link and is
initialized by software/BIOS. This will correspond to the device number for
each port.
port 0- device number of 0 (ESI)
port 2 - device number of 2
port 3 - device number of 3
port 4 - device number of 4
port 5- device number of 5
port 6- device number of 6
port 7- device number of 7
Reserved
L1EL: L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express* port. It
indicates the length of time this port requires to complete transition from L1
to L0.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64 µs
The Intel
set to the maximum value for safety
L0sEL: L0s Exit Latency
This field indicates the L0s exit latency (i.e., L0s to L0) for the PCI Express*
port.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that the Intel
implementation and for safety, this field is set to the maximum value.
ACTPMS: Active State Link PM Support
This field indicates the level of active state power management supported on
the given PCI Express* port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
The Intel
Management but it does permit a downstream device from placing the link in
L0s
®
®
5100 MCH Chipset does not support L1 acceptable latency and is
5100 MCH Chipset does not initiate L0s active state Power
®
5100 MCH Chipset does not support L0s exit latency
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
145