HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 20

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
20
January 2008
October 2007
®
Date
5100 Memory Controller Hub Chipset
Revision Description
002
001
Global Changes:
Register Changes:
Functional Description:
Others:
Initial release
• Added remaining DMA Engine capabilities to document.
• Removed A0 silicon descriptive text.
• Corrected references to “Dual Channel mode” with proper reference of “two channels;” Dual
• Corrected spelling and grammar where appropriate.
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• Section 1.3.1, “BIOS SelfTest Utility” removed; SelfTest password is no longer required.
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Channel mode does not exist on the MCH.
Section 3.8.3.11, “EXSMRAMC - Expansion System Management RAM Control Register”
corrected Function number typo from 2 to 0.
Section 3.8.3.7, “PAM6 - Programmable Attribute Map Register 6”
ESIENABLE6 address range.
Section 3.8.13.11, “EMASK_FSB[1:0]: FSB Error Mask Register”
Section 3.9.1.4, “MCDEF3: MCDEF Register 3”
Asynchronous Request for Self-refresh to White Paper under development.
Section 3.9.10.1, “DSRETC[1:0]: DRAM Self-Refresh Extended Timing and Control”
introductory paragraph TRFC value for 32 GB mode of operation and corrected name of
Register bits to better reflect their function.
Section 5.2.2, “DIMM Technology and Organization”
and associated 32 GB mode diagram.
Section 5.2.3.1, “Permissible Configurations”
between channels when added single ranks.
Section 5.2.4, “Memory RAS”
Section 5.2.6.1, “Inbound ECC Code Layout for Memory Interface”
description.
Section 5.2.8.2, “Open Loop Global Throttling”
Section 5.2.9, “Electrical Throttling”
of DIMM
Section 5.4, “XAPIC Interrupt Message Delivery”
signal references in all subsections accordingly.
Section 5.8, “Software Guidance for MSI Handling”
Clarification #1.
Section 5.10, “Interrupt Swizzling”
Section 5.13.9, “DMA Engine Implementation,” Section 5.13.10, “DMA Engine Usage Model,”
Section 5.14, “Using DMA Engine Technology,” Section 5.15, “Implementation Requirements,”
Section 5.16, “Programming Flow”
Engine information.
Section 5.20.2, “SMBus and PCI Express* Interoperability Timeout Recommendation”
from SU revision 001, Specification Clarification #2.
Section 5.20.10, “Virtual Pin Ports”
Section 5.24, “Error List,” Table 123, “Intel® 5100 Memory Controller Hub Chipset Error List”
added DMA Errors to Error List table.
Section 1.3, “Intel® 5100 Memory Controller Hub Chipset Overview,”
DIMM support.
Section 2.7, “Clocks, Reset and Miscellaneous”
descriptions.
Section 6.1.2, “Power Characteristics,” Section 125, “Operating Condition Power Supply Rails”
updated note 8.
Technology”.
corrected to indicate rank sparing not DIMM sparing.
and
added.
cleaned up text description.
updated
Section 5.17, “DMA Engine Driver”
Table 91, “Electrical Throttle Window as Function
added impact of mixing number of ranks
changed Register to reserved, moved
rewrote subsection.
updated 48GB_Mode and ASYNCRFSH signal
Intel
added nomenclature explanation and updated
added from SU revision 001, Specification
updated DIMM Configuration descriptions
®
5100 MCH Chipset—Revision History
Order Number: 318378-005US
added note on parity.
corrected error in
updated title and
added four rank per
added for DMA
updated
July 2009
added