HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 24

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 1.
Intel
Datasheet
24
®
5100 Memory Controller Hub Chipset
Terminology (Sheet 2 of 6)
Delayed
Transaction
DID
DIMM
DIMM Rank
Downstream
DRAM Page
(Row)
Dword
ECC
ESI
Flit
FSB
Full Duplex
Gb/s
GB/s
Half Duplex
Hardwired
Host
I/O
ICH9R
Implicit
Writeback
Inband
Inbound
Inbound (IB)/
Outbound (OB),
AKA Upstream/
DownStream,
Northbound/
Southbound,
Upbound/
Downbound
Incoming
Initiator
Terminology
A transaction where the target retries an initial request, but without notification to the
initiator, forwards or services the request on behalf of the initiator and stores the
completion or the result of the request. The original initiator subsequently re-issues the
request and receives the stored completion
Device Identification. Provides PCI device identification number.
Dual-in-Line Memory Module. A packaging arrangement of memory devices on a
socketable substrate.
That set of SDRAMs on one branch which provides the data packet
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
The DRAM cells selected by the Row Address.
A reference to 32 bits of data on a naturally aligned four-byte boundary (i.e., the least
significant two bits of the address are 00b).
Error Correcting Code
Enterprise South Bridge Interface. The interface connecting the MCH to the ICH9R.
The exchange of the unit of information at the link layer that synchronizes each data
transfer, i.e., flow control with the use of credits. Flits are usually several phits long.
Processor Front-Side Bus. This is the bus that connects the processor to the MCH.
A connection or channel that allows data or messages to be transmitted in opposite
directions simultaneously.
Gigabits per second (10
Gigabytes per second (10
A connection or channel that allows data or messages to be transmitted in either
direction, but not simultaneously.
A parameter that has a fixed value.
This term is used synonymously with processor.
1.
2.
Ninth generation I/O controller hub with RAID, the Intel
The I/O controller hub component that contains the legacy I/O functions. It communicates
with the MCH over a proprietary interconnect called the ESI interface.
A snoop initiated data transfer from the bus agent with the modified Cache Line to the
memory controller due to an access to that line.
Communication that is multiplexed on the standard lines of an interface, rather than
requiring a dedicated signal.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
Up, North, or Inbound is in the direction of the processor, Down, South, or Outbound is in
the direction of I/O (SDRAM, SMBus).
A transaction or data that enters the MCH.
The source of requests. An agent sending a request packet on PCI Express* is referred to
as the Initiator for that transaction. The Initiator may receive a completion for the
request.
Input/Output.
When used as a qualifier to a transaction type, specifies that transaction targets
Intel
®
architecture-specific I/O space. (e.g., I/O read)
9
bits per second).
9
bytes per second).
Description
Intel
®
5100 MCH Chipset—Introduction
®
82801IR I/O Controller Hub.
Order Number: 318378-005US
July 2009