HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 223

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.3
3.11.4
July 2009
Order Number: 318378-005US
CCR: Class Code Register
1. A peripheral device in this case denotes an integrated device in the root complex.
The bits in this register are writable once by BIOS in order to allow the device to be
programmable either as an OS-visible device [088000h] (implementing a driver) or a
chipset host bridge device [060000h] (relying on BIOS code and/or pure hardware
control for programming the DMA Engine registers). The default value of the CCR is set
to 088000h (corresponding to an integrated device in the root port).
CB_BAR: DMA Engine Base Address Register
This DMA Engine base address register marks the memory-mapped registers used for
the DMA functionality.
Device:
Function:
Offset:
23:16
15:8
7:0
Device:
Function:
Offset:
63:40
39:10
9:4
3
2:1
0
Bit
Bit
RWO
RWO
RWO
RO
RW
RV
RO
RO
RO
Attr
Attr
®
5100 MCH Chipset
8
0
09h
8
0
10h
08h
80h
0h
0h
003F9C00h
0h
0
10
0
Default
Default
CB_BASE_Win_Upper: Upper DMABase Window:
The upper bits of the 64-bit addressable space are initialized to 0 as default
and is unusable in the Intel
CB_BASE_WIN: DMABase Window
This marks the 1 kB memory-mapped registers used for the chipset DMA and
can be placed in any MMIO region (low/high) within the physical limits of the
system. For instance, the Intel
addressable space. Hence bits 39:10 are assumed to be valid and also contains
the default value of the CB_BAR in the FE70_0000h to FE70_03FFh range.
Reserved
Pref: Prefetchable
The DMA registers are not prefetchable.
Type: Type
The DMA registers is 64-bit address space and can be placed anywhere within
the addressable region of the Intel
Mem_space: Memory Space
This Base Address Register indicates memory space.
Base Class Code: A 08h code indicates that the DMA Engine device is a
peripheral device
Default: 08h
Sub-Class Code: An 80h code indicates that the DMA Engine device is a non-
specific peripheral device. A 00h code is used to indicate a Host bridge device.
Default: 80h
Register-Level Programming Interface: This field identifies a default value
for non-specific programming requirements.
1
. A 06h code is used to indicate a Host bridge device.
®
5100 MCH Chipset.
®
Description
5100 MCH Chipset uses only 40-bit
Description
®
Intel
5100 MCH Chipset (up to 40-bits).
®
5100 Memory Controller Hub Chipset
Datasheet
223