HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 389

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Testability—Intel
7.1.3
Table 138.
7.1.4
7.1.5
July 2009
Order Number: 318378-005US
Shift-DR: The Data Register connected between TDI and TDO as a result of selection
by the current instruction is shifted one stage toward its serial output on each rising
edge of TCK. The output arrives at TDO on the falling edge of TCK. The parallel, latched
output of the selected Data Register does not change while new data is being shifted in.
Pause-DR: Allows shifting of the selected Data Register to be temporarily halted
without stopping TCK. All registers retain their previous values.
Update-DR: Data from the shift register path is loaded into the latched parallel
outputs of the selected Data Register (if applicable) on the falling edge of TCK. This and
Test-Logic-Reset are the only controller states in which the latched paralleled outputs of
a data register can change.
All other states are temporary controller states, used to advance the controller between
active states. During such temporary states, all test registers retain their prior values.
Reset Behavior of TAP
The TAP and its related hardware are reset by transitioning the TAP controller finite
state machine into the Test-Logic-Reset state. Once in this state, all of the reset actions
listed in
upon reset (i.e., by resetting the TAP, the device will function as though the TAP did not
exist).
TAP Reset Actions
The TAP can be transitioned to the Test-Logic-Reset state in one of two ways:
Cycling power on a device does not ensure that the TAP is reset. System designers
must utilize one of the two methods stated above to reset the TAP. The method used
depends on the manufacturing and debug requirements of the system.
Clocking TAP
There is no minimum frequency at which the Intel
Because the private chains are synchronized to the local core clock of that chain there
is a maximum rate relative to the core that the interface can operate. The ratio is 12:1
providing a maximum rate of 27 MHz for a core frequency of 333 MHz.
Accessing Instruction Register
Figure 57, “TAP Instruction Register”
the TAP instruction register. This register consists of a 7-bit shift register (connected
between TDI and TDO), and the actual instruction register (which is loaded in parallel
from the shift register). The parallel output of the TAP instruction register goes to the
TAP instruction decoder.
®
TAP instruction register
Boundary scan logic
TDO pin
• Assert the TRST# pin at any time. This asynchronously resets the TAP controller.
• Hold the TMS pin high for five consecutive cycles of TCK. This is guaranteed to
5100 MCH Chipset
TAP Logic Affected
transition the TAP controller to the Test-Logic-Reset state on a rising edge of TCK.
Figure 138, “TAP Reset Actions”
TAP Reset State Action
Tristated
Disabled
IDCODE
shows the (simplified) physical implementation of
are performed. The TAP is completely disabled
®
(instr equivalent to reset is highlighted)
5100 MCH Chipset TAP will operate.
Intel
®
Related TAP Instructions
5100 Memory Controller Hub Chipset
EXTEST
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Datasheet
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