HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 318

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.13.6.3
5.13.6.4
5.13.7
Note:
Intel
Datasheet
318
®
5100 Memory Controller Hub Chipset
Link Level Retry
The PCI Express* Base Specification, Rev. 1.0a lists all the conditions where a packet
gets negative acknowledged. One example is on a CRC error. The link layer in the
receiver is responsible for calculating 32-bit CRC (using the polynomial defined in the
PCI Express* Base Specification, Rev. 1.0a) for incoming packets and comparing the
calculated CRC with the received CRC. If they do not match, then the packet is retried
by negative acknowledging the packet with a NAK DLLP and specifying the sequence
number of the last good packet. Subsequent packets are dropped until the reattempted
packet is observed again.
When the transmitter receives the NAK, it is responsible for retransmitting the packet.
Furthermore, any packets sent after the last good packet will also be resent since the
receiver has dropped any packets after the corrupt packet.
The transmitter keeps track of packets that have been sent but not acknowledged
through the use of a retry buffer. Transactions are added to the buffer as they are on
the PCI Express* port. Transactions are removed from the buffer after they have been
acknowledged by the receiver.
ACK Timeout
Packets can get “lost” if the packet is corrupted such that the receiver’s physical layer
does not detect the framing symbols properly. Normally, lost packets are detectable
with non-linearly incrementing sequence numbers. A timeout mechanism exists to
detect (and bound) cases where the last packet sent (over a long period of time) was
corrupted. A replay timer bounds the time a retry buffer entry waits for an ACK or NAK.
Refer to the PCI Express* Base Specification, Rev. 1.0a for details on this mechanism
for the discussion on Retry Management and the recommended timer values.
Flow Control
The PCI Express* mechanism for flow control is credit-based and only applies to TLPs.
DLLP packets do not consume any credits. Through initial hardware negotiation and
subsequent updates, a PCI Express* transmitter is aware of the credit capabilities of
the interfacing device. A PCI Express* requester will never issue a transaction when
there are not enough advertised credits in the other component to support that
transaction. If there are not enough credits, the requester will hold off that transaction
until enough credits free up to support the transaction. If the ordering rules and
available credits allow other subsequent transactions to proceed, the MCH will allow
those transactions.
For example, assume that there are no Non-Posted Request Header Credits (NPRH)
credits remaining and a memory write is the next transaction in the queue. PCI
Express* ordering rules allow posted writes to pass reads. Therefore, the Intel
MCH Chipset will issue the memory write. Subsequent memory reads from the source
device must wait until enough NPRH credits free up.
Flow control is orthogonal with packet ACKs.
The PCI Express* flow control credit types are described in
Credit Mapping for Inbound Transactions.”
1.0a defines which TLPs are covered by each flow control type.
The PCI Express* Base Specification, Rev.
Intel
®
5100 MCH Chipset—Functional Description
Table 98, “PCI Express*
Order Number: 318378-005US
®
July 2009
5100