HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 315

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.13.5.4
Figure 30.
5.13.5.5
July 2009
Order Number: 318378-005US
The elastic buffer is eight symbols deep. This accounts for three clocks of
synchronization delay, the longest possible TLP allowed by the Intel
Chipset (256 bytes), a 600 ppm difference between transmitter and receiver clocks,
and worst case skip ordered sequence interval of 1538, framing overheads, and a few
symbols of margin.
Deskew Buffer
Every PCI Express* port implements a deskew buffer. The deskew buffer compensates
for the different arrival times for each of the symbols that make up a character. The
outputs of the deskew buffer is the data path fed into the Link layer.
PCI Express* Deskew Buffer (4x Example)
At reset, the delay of each lane in the deskew buffer is adjusted so that the symbols on
each lane are aligned. The receiver must compensate for the allowable skew between
lanes within a multi-lane link before delivering the data and control to the data link
layer. The deskew buffer is eight symbols deep to compensate for up to 20 ns of skew
between lanes.
Lane Width Connections
The PCI Express* ports between the MCH and the PCI Express* connector can be
connected straight through or reversed. The degradation lanes for specific port widths
are specified in this section as well, i.e., when it is not possible to train to the highest
configured lane width, the link reduces the lane width for either straight through or
reversed connections. The specific port widths supported are the lane connections as
depicted in
Matrix”. As an example of a straight through connection and the associated
degradation, when Port 4 through Port 7 are configured as a x16 port, lane 0 through
lane 15 of the MCH can be connected to lane 0 through lane 15 of the PCI Express*
connector or PCI Express* link partner. If the connection does not support the x16 link,
a x8 link may be established using lane 0 through lane 7 of the MCH and lane 0 through
lane 7 of the link partner. If the connection does not support the x8 link, a x4 link may
®
Table 97, “Intel® 5100 Memory Controller Hub Chipset Lane Reversal
5100 MCH Chipset
Elastic Buffer
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
315