HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 143

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
Bit
7:5
4
3
2
1
0
®
Attr
RW
RW
RW
RW
RW
RO
5100 MCH Chipset
7-2, 0
0
74h
Default
000
0
0
0
0
0
MPS: Max Payload Size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express* port. As a receiver, the Intel
handle TLPs as large as the set value. As a transmitter, it must not generate
TLPs exceeding the set value. Permissible values that can be programmed
are indicated by the Max_Payload_Size_Supported in the Device Capabilities
register:
000: 128 bytes max payload size
001: 256 bytes max payload size
010: 512 bytes max payload size
011: 1024 bytes max payload size
100: 2048 bytes max payload size
101: 4096 bytes max payload size
others: Reserved
Note:
Note:
ENRORD: Enable Relaxed Ordering
The Intel
this bit is initialized to ‘0’
URREN: Unsupported Request Reporting Enable
This bit controls the reporting of unsupported requests to the MCH in the PCI
Express* port.
0: Unsupported request reporting is disabled
1: Unsupported request reporting is enabled
Note that the reporting of error messages (such as ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by PCI Express* port is controlled
exclusively by the PCI Express* Root Control register (PEXRTCTRL) described
in
Register.”
FERE: Fatal Error Reporting Enable
This bit controls the reporting of fatal errors internal to the MCH in the PCI
Express* port.
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
NFERE: Non Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the MCH in the
PCI Express* port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the MCH in the
PCI Express* port.
0: Correctable error reporting is disabled
1: Correctable error reporting is enabled
Section 3.8.11.12, “PEXRTCTRL[7:2,0] - PCI Express* Root Control
The MCH supports max payload sizes only up to 256 bytes. If
Software programs a value that exceeds 256 bytes for the MPS field,
then it will be considered as an error. For receive TLPs, it will be
flagged as “unsupported request” and for transmit TLPs, it will be
recorded as a Malformed TLP.
Due to erratum #12 of the Intel
Chipset Specification Update, order number 318385, read
completion coalescing cannot be used if MPS=256 bytes is set by
software. Read completion combining up to 128 bytes would work
only if the MPS is set by software. Read completion combining up to
128 bytes would work only if the MPS is set to 128 bytes. See
PEXCTRL.COALESCE_EN field.
®
5100 MCH Chipset enforces only strict ordering only and hence
Description
Intel
®
®
5100 Memory Controller Hub Chipset
5100 Memory Controller Hub
®
5100 MCH Chipset must
Datasheet
143