HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 128

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 54.
3.8.8.30
3.8.8.31
Intel
Datasheet
128
®
5100 Memory Controller Hub Chipset
GIO Port Mode Selection (Sheet 2 of 2)
CBPRES: DMA Engine Present Control Register
This register provides control for suppressing access to the configuration space of
selected devices within the Intel
disable DMA Engine configuration and memory mapped operations to device 8, function
0 and device 8, function 1 respectively. This is a special register intended to suppress
the “yellow-bang” warning for the DMA Engine device for Intel
customers who install non-standard operating systems without associated drivers. It
can also be used as a defeature mode to block DMA Engine technology from being
used.
PEXCTRL[7:2,0]: PCI Express* Control Register
Device:
Function:
Offset:
Device:
Function:
Offset:
3'b011
3'b100
3'b101
3'b110
3'b111
GPMNXT0[2:0]
31:26
15:1
Bit
Bit
0
(IOU0)
Attr
RW
RWO
Attr
0
0
44h
7-2,0
0
48h
RV
GIO Port (IOU0)
invalid
invalid
invalid
invalid
x4
Port0
(ESI)
Default
Default
0h
RSVD
(RSVD)
Port1
0
0
Reserved
Reserved
CB_CFG_ENABLE: DMA Engine Configuration Enable
1: Enable Configuration/Memory mapped accesses to the DMA Engine
configuration space located in Device 8, Fn 0.
0: Disable DMA Engine configuration accesses to Device 8, Fn 0 and Fn
1. The Intel
Engine configuration/memory mapped space.
Auto
Negoti
ation
Port2
®
5100 MCH Chipset. Specifically, the BIOS can enable/
Port3
®
5100 MCH Chipset will master abort requests to the DMA
GPMNXT1[2:0]
3'b011
3'b100
3'b101
3'b110
3'b111
Intel
(IOU1)
®
5100 MCH Chipset—Register Description
Description
Description
GIO Port (IOU1)
x8
x16
invalid
invalid
Auto
Negoti
ation
Port4
®
Order Number: 318378-005US
5100 MCH Chipset
N/A
N/A
Port5
x8
N/A
Port6
July 2009
N/A
N/A
Port7