HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 206

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.6.11
3.9.6.12
Table 67.
Intel
Datasheet
206
®
5100 Memory Controller Hub Chipset
REDMEMA[1:0]: Recoverable Memory Data Error Log Register A
This register latches information on the first detected correctable ECC error.
REDMEMB[1:0]: Recoverable Memory Data Error Log Register B
This register latches information on the first detected ECC error. Note that the
ECC_locator field in this register is valid only when the corresponding FERR_NF_MEM
register bits are set.
ECC Locator Mapping Information (Sheet 1 of 2)
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
30:29
28:16
31:18
15:0
31:0
17:0
Bit
Bit
Bit
31
DS[11:10]
DS[13:12]
DS[15:14]
Symbols
DS[1:0]
DS[3:2]
DS[5:4]
DS[7:6]
DS[9:8]
ROST
ROST
ROST
ROST
ROST
Attr
Attr
Attr
RV
RV
22, 21
0
194h
22, 21
0
198h
22, 21
0
19Ch
Default
Default
Default
000h
00
0h
0h
0h
0
0
RDWR (should always be 0)
‘0’ = Read
‘1’ = Write
Reserved
CAS: CAS address of the failed request
The CAS address will map from 12:0 while bit 10 (autoprecharge) is
hardwired to 0.
RAS: RAS address of the failed request
SYNDROME:
Reserved
ECC_Locator: identifies the adjacent symbol pair in error for correctable
errors according to
Section 5.2.6.1, “Inbound ECC Code Layout for Memory Interface”
DQS Lane
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
Table 67, “ECC Locator Mapping Information”
Intel
DQ[19:16]
DQ[27:24]
DQ[35:32]
DQ[43:40]
DQ[51:48]
DQ[59:56]
®
DQ[11:8]
DQ Lane
DQ[3:0]
Description
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
Locator Bit
0
1
2
3
4
5
6
7
and
July 2009