HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 244

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.23
3.11.23.1
Intel
Datasheet
244
1. The channel specific system error mask register has been defined in the general debug register
1. An example would be an illegal write address to reserved space (firmware) that causes the
®
area for lack of debug space in the channel registers.
system to crash (blue-screen in windows OS)
5100 Memory Controller Hub Chipset
specific error does not cause error signaling. Software decides which DMA errors are
fatal
system error signaling.
DMA Channel Specific Registers
As described in
locations starting from offset 80h of the CB_BAR register (see
separated by 128 bytes for each channel. They are located in Bus 0, Device 1, Function
1 at the offsets shown in
DMA_COMP[3:0]: DMA Compatibility Register
Offset:
31:16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset:
15:1
Bit
Bit
0
1
to the system and can set them accordingly. The default value is to disable the
RV
RO
RO
RWST
RWST
RWST
RWST
RWST
RWST
RO
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
RO
RV
Attr
4Ch, 48h, 44h, 40h
202h, 182h, 102h, 82h
Default
0h
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table
Default
0h
1
71, the DMA channel specific information is contained in four
Reserved
v1_comp: v1 Compatibility
The DMA operation is compatible with software written for version 1 of the DMA
Engine Specification and hence it is set to ‘1’ by the chipset.
Reserved
Unaffil_err_Msk: Unaffiliated Error Mask
Soft_err_Msk: Soft Error Mask
int_cfg_err_Msk: Interrupt Configuration Error Mask
Cmp_addr_err_Msk: Completion Address Error Mask
Desc_len_err_Msk: Descriptor Length Error Mask
Desc_ctrl_err_Msk: Descriptor Control Error Mask
Wr_data_err_Msk: Write Data Error Mask
Rd_data_err_Msk: Read Data Error Mask
DMA_data_par_err_Mskr: DMA Data Parity Error Mask
Cdata_par_err_Msk: Chipset Data Parity Error Mask
Chancmd_err_Msk: CHANCMD Error Mask
Chn_addr_val_err_Msk: Chain Address Value Error Mask
Desc_err_Msk: Descriptor Error Mask
Nxt_desc_addr_err_Msk: Next Descriptor Address Error Mask
DMA_xfrer_daddr_err_Msk: DMA Transfer Destination Address Error Mask
DMA_trans_saddr_err_Msk: DMA Transfer Source Address Error Mask
Section 3.11.
Intel
Description
Description
®
5100 MCH Chipset—Register Description
Section
Order Number: 318378-005US
3.11.4) and
July 2009