HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 215

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
26:24
23:16
15:8
7:1
Bit
27
0
RWST
RWST
RWST
RWST
RWST
Attr
RV
®
5100 MCH Chipset
16
1
4Ch
Default
000
00h
00h
0h
1
0
CKOVRD: Clock Over-ride.
‘0’ = Clock signal is driven low, overriding writing a ‘1’ to CMD.
‘1’ = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to “budge” the port out of a “stuck” state.
SA: Slave Address.
This field identifies the DIMM EEPROM to be accessed through the SPD register.
BA: Byte Address.
This field identifies the byte address to be accessed through the SPD register.
DATA: Data.
Holds data to be written by SPDW commands.
Reserved
CMD: Command.
Writing a ‘0’ to this bit initiates an SPDR command. Writing a ‘1’ to this bit initiates
an SPDW command.
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
215