HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 158

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.3
Intel
Datasheet
158
®
5100 Memory Controller Hub Chipset
UNCERRSTS[0] - Uncorrectable Error Status For ESI Port
This register identifies uncorrectable errors detected on ESI Port. If an error occurs and
is unmasked in the detect register (EMASK_UNCOR_PEX), the appropriate error bit will
be recorded in this register. If an error is recorded in the UNCERRSTS register and the
appropriate bit (along with the severity bit of the UNCERRSEV register) determines
which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR, PEX_FAT_NERR,
PEX_NF_COR_NERR registers get recorded. These error log registers are described
starting from
Register.”
Device:
Function:
Offset:
Device:
Function:
Offset:
31:22
11:6
11:6
3:1
Bit
Bit
17
16
15
14
13
12
21
20
19
18
17
16
15
14
13
12
5
4
0
5
4
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWST
RWST
Attr
Attr
2-3, 4-7
0
104h
0
0
104h
RV
RV
RV
RV
RV
Section 3.8.12.24, “PEX_FAT_FERR[7:2,0] - PCI Express* First Fatal Error
Default
Default
0h
0h
0
0
0
0
0
0
0
0
0
0
0
0
0h
0h
0
0
0
0
0
0
0
0
0
Reserved
IO18Err: ESI Reset timeout
IO2Err: Received an Unsupported Request
Reserved
IO9Err: Malformed TLP Status
IO10Err: Receiver Buffer Overflow Status
IO8Err: Unexpected Completion Status
IO7Err: Completer Abort Status
IO6Err: Completion Timeout Status
IO5Err: Flow Control Protocol Error Status
IO4Err: Poisoned TLP Status
Reserved
IOErr: Surprise Link-down Error Status
IO0Err: Data Link Protocol Error Status
IO10Err: Receiver Buffer Overflow Status
IO8Err: Unexpected Completion Status
IO7Err: Completer Abort Status
IO6Err: Completion Timeout Status
IO5Err: Flow Control Protocol Error Status
IO4Err: Poisoned TLP Status
Reserved
IO19Err: Surprise Link-down Error Status
IO0Err: Data Link Protocol Error Status
Reserved
IO3Err: Training Error Status
This field should not be used for obtaining Training error status due to a
recent PCI Express* Base Specification, Rev. 1.0a Errata Dec 2003 to
remove training error.
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Order Number: 318378-005US
July 2009