HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 365

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 118.
Note:
5.22
5.22.1
July 2009
Order Number: 318378-005US
Decode Table in Intel
The Intel
originate from the FSB targeting the FED4_0xxxh range (ring 0) access to an
appropriate Read/Write memory cycle of zero length on ESI. It is the responsibility of
the Intel
internally complete the transaction back to the Intel
the Intel
or address alignment restrictions for these MMIO reads/writes when they are mapped
to transactions on ESI. They are passed through as they appear on FSB but as
transactions on the ESI. The Intel
UC) for these CPU accesses but it is the responsibility of the software to employ the
correct attributes as the case may be and should be cognizant of the inherent ordering/
serialization issues in the CPU. These requests are deferred on the FSB by the Intel
5100 MCH Chipset, and it is entered into the ordering domain only after it is placed in
IOU for dispatch to the ESI port. Also note that the ESI port in the Intel
Chipset does not support Chipset Write coalescing (CSWC) (that is, does not combine
smaller packets to form a larger TLP).
It is recommended that software use the “UC” attribute for the FED4_0xxxh range.
Clocking
The following sections describe the Intel
Reference Clocks
The BUSCLK, and CORECLK (herein referred to “in aggregate” as “BUSCLK”) reference
clocks, operating at 266/333 MHz, are supplied to the Intel
are the processor bus, core, and PLL reference clocks. This frequency is common
between all processor bus agents. Phase matching between agents is required. The two
processor FSBs operate in phase with the core clock.
The CH(0/1)_DCLK reference clocks, (herein referred to as DDRCLK) operating at half
the DDR2 frequency (operating at the SDRAM command-clock frequency) are supplied
by the Intel
The PECLK reference clock, operating at 100 MHz, is supplied to the Intel
Chipset. This is the PCI Express* PLL reference clock. The PCI Express* flit PLL outputs
250 MHz. The PCI Express* phit PLL outputs 2.5 GHz. The phit clock frequency must be
tightly matched (mesochronous mode) between both PCI Express* agents when
spectrum-spreading is not employed. The phit clock frequency is common to both PCI
Express* agents when spectrum-spreading is employed. When the phit clock frequency
FED4_0000 - FED4_0FFF
FED4_1000 - FED4_1FFF
FED4_2000 - FED4_2FFF
FED4_3000 - FED4_3FFF
FED4_4000 - FED4_4FFF
Address Range
®
®
®
(Locality 0)
(Locality 1)
(Locality 2)
(Locality 3)
(Locality 4)
®
82801IR I/O Controller Hub to convert these transactions appropriately or
5100 MCH Chipset as a component does not impose any transaction length
5100 MCH Chipset will forward zero length MMIO read/write requests that
®
5100 MCH Chipset
5100 MCH Chipset to the DIMMs.
®
5100 Memory Controller Hub Chipset for TPM Locality
Transactions on FSB
®
Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
5100 MCH Chipset supports attribute aliasing (WC,
®
5100 MCH Chipset clocks.
®
Intel
5100 MCH Chipset. In addition,
®
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset. These
Transactions on ESI
(Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
Memory Rd/Write
for Peer-to-peer)
Read/Write
®
®
5100 MCH
5100 MCH
Datasheet
®
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