HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 288

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.2.8.2
5.2.8.3
Note:
Intel
Datasheet
288
®
5100 Memory Controller Hub Chipset
Open Loop Global Throttling
In the open loop global throttling window scheme, the number of activations per rank is
counted for a large time period called the “Global Throttling window”. The Global
throttling window is chosen as an integral multiple of 1344 MCH core clocks (the
thermal throttling window or throttling activation window). The internal core clocks are
used for calculating the windows and not the DDR clocks. Under normal operating
conditions, the Global Throttling Window is 0.65625x2
translates to 16384x1344 clocks, approximately 66.06 ms for DDR2-667 and 82.58 ms
for DDR2-533.
During the Global throttling window, the number of activations is counted for each rank
(24-bit counters are required). Normally the throttling logic throttles at a “low” level
using the THRTLOW register. However, if the number exceeds the number indicated by
the GBLACT.GBLACTLM register defined in
Registers”, then the THRTSTS[1:0].GBLTHRT bit is set for the respective channel at the
end of the current Global Throttling window, causing the activation throttling logic to
throttle at a “high” level using the THRTHIGH register. The THRTSTS[1:0].GBLTHRT will
remain active until 16 (or two) global throttling windows in a row have passed without
any rank exceeding the GBLACTLM value; whereupon, the Memory Controller indicates
the end of the high throttling period by clearing the THRTSTS[1:0].GBLTHRT register
field and returning to the use of the THRTLOW register for activation throttling.
If part way through the count of 16 (or two) global throttling windows, the
GBLACT.GBLACTLM is again exceeded within one Global Throttle Window, the counter
gets reset and it will once again count 16 (or two) global throttle windows throttling at
the THRTHIGH level.
If the number of activations to a rank exceeds the limit specified by the register within
a given throttling activation window, then further requests are blocked and CKE will be
driven low to the affected rank for the remainder of the throttling activation window.
The global throttling window prevents shorts peaks in bandwidth from causing
activation throttling when there has not been sufficient DRAM activity over a long
period of time to warrant throttling at the high level.
Global Activation Throttling Software Usage
In practice, the throttle settings for THRTHIGH are likely to be set by BIOS such that
the memory controller throttle logic will actually prevent the GBLACT limit from being
exceeded. The THRTLOW is often used as a Global Throttle Window, where the
GBLACT.GBLACTLM is exceeded, causing the MC to use a larger throttling period
THRTHIGH for 16 (or two) global windows. During each of those global windows,
GBLACT limit is not exceeded, because the throttling will prevent it from being
exceeded. After 16 (or two) global throttling windows, it switches back to THRTLOW,
and on the next global window GBLACT is again exceeded, causing another 16 (or two)
windows. Hence, a cumulative pattern of 16, 1, 16, 1 (or 2, 1, 2, 1) global throttling
windows occur preventing excessive heat dissipation in the DIMMs by prolonging the
throttle period.
It should be mentioned that the throttling control policies implemented on the Intel
5100 MCH Chipset use the internal core clocks for the calculating the windows and not
the DDR clocks. Thus any software/BIOS should take this into account for manipulating
the THRTSTS.THRMTHRT register bit value when dealing with different technologies
and speeds.
Section 3.9.2, “Memory Throttling Control
Intel
®
5100 MCH Chipset—Functional Description
25
clocks in duration which
Order Number: 318378-005US
July 2009
®