HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 371

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 123.
July 2009
Order Number: 318378-005US
DMA8
DMA9
DMA10
DMA11
DMA12
DMA13
Notes:
1.
2.
ERR #
MCH
in
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
Read Data error
Write Data error
Descriptor
Control Error
Descriptor
length Error
Completion
Address Error
Interrupt
Configuration
Error
Error Name
Intel
®
5100 Memory Controller Hub Chipset Error List (Sheet 3 of 7)
The DMA channel sets this
bit indicating that a read
could not be completed
(e.g., starvation).
The DMA channel sets this
bit indicating that a write
was unable to be
completed at the
destination (e.g., no space
available in DM).
The DMA channel sets this
bit indicating that the
current descriptor has an
illegal control field value in
the “desc_control” field.
The DMA channel sets this
bit indicating that the
current transfer has an
illegal length field value
The DMA channel sets this
bit indicating that the
completion address
register was configured to
an illegal address
The DMA channel sets this
bit indicating that the
interrupt related registers
were not configured
properly and an interrupt
could not be generated
®
5100 MCH Chipset
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
Definition
Error
Type
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
by taking a snap shot of the
the runtime addresses that
SADDR and DADDR will be
when an error is met. The
respective register fields
NERR_TRANSFER_SIZE,
FERR_TRANSFER_SIZE,
NERR_DESC_CTRL,
FERR_DESC_CTRL,
the DMA Engine is
NERR_CHANCMD,
NERR_CHANERR/
FERR_CHANCMD,
FERR_CHANERR/
NERR_CHANCMP
FERR_CHANCMP
NERR_DADDR,
NERR_NADDR,
FERR_DADDR,
FERR_NADDR,
NERR_SADDR,
FERR_SADDR,
Log Register
executing
Log
Intel
®
5100 Memory Controller Hub Chipset
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Halt DMA Engine
Cause/Actions
Datasheet
371