HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 242

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.22.5
3.11.22.6
Intel
Datasheet
242
1. Offsets are calculated from the base address of the CB_BAR register defined in
®
“CB_BAR: DMA Engine Base Address Register” on page
5100 Memory Controller Hub Chipset
1. Reading this register clears all of the bits.
CBVER - DMA Engine Version
The DMA Engine version register field indicates the version of the DMA Engine
specification that the MCH implements. The most significant 4-bits (range 7:4) are the
major version number and the least significant 4-bits (range 3:0) are the minor version
number. The MCH implementation for this DMA Engine version is 1.0 encoded as 0001
0000b.
PERPORT_OFFSET - Per-port Offset
For each PCI Express* port that has DMA Engine capabilities there is a block of per-port
registers in the DMA Engine device’s MMIO space. The per-port offset
location of the first set of per-port registers residing in the MMIO space. This register
points to the first set and each set contains a pointer to the next set of per-port
registers. This provides the means for S/W to locate all of the per-port MMIO register
sets.
Offset:
3:0
Offset:
7:4
3:0
Offset:
15:2
1:0
Bit
Bit
Bit
RC
RO
RO
RO
RV
Attr
Attr
Attr
1
04h
08h
0Ah
0h
1h
2h
00C0h
0h
Default
Default
Default
ChanAttn: Channel Attention
Each bit specifies the interrupt status of each DMA channel. Bit 0 represents
channel 0, bit 1 represents channel 1, etc. These bits are OR’d together to provide
the legacy interrupt signal.
When a DMA channel generates an interrupt and its CHANCTL Interrupt Disable bit
is not set, the hardware sets this bit. The software (interrupt service routine) reads
these bits to learn which channels are generating the interrupt, and calls the
controlling process(es). A channel that has generated an interrupt can not generate
another interrupt until the controlling process clears the channel’s Interrupt Disable
bit in its CHANCTL register. The hardware automatically clears all ATTNSTATUS bits
when software reads this register, writing this register has no effect.
MJRVER: Major Version
Specifies Major version of the DMA Engine implementation. Current value is 1h
MNRVER: Minor Version
Specifies Minor version of the DMA Engine implementation. Current value is 2h
Fst_PPR_OFF:
Points to the first set of Per-port registers. A value of zero means that there are no
per-port CB resources. Since the per port offset is 32-bit aligned, the effective
address is calculated by concatenating “00C0h” ((bits 8, 9 are ‘1’s) with “00b”
giving 300h as an offset from CB_BAR and this locates the port priority registers for
port 2 in the map.
Reserved
223.
Intel
Description
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
Section 3.11.4,
1
indicates the
July 2009