HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 390

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Figure 57.
Figure 58.
Intel
Datasheet
390
®
5100 Memory Controller Hub Chipset
TAP Instruction Register
Figure 58, “TAP Instruction Register Operation”
register during the Capture-IR, Shift-IR and Update-IR states. Shaded areas indicate
the bits that are updated. In Capture-IR, the shift register portion of the instruction
register is loaded in parallel with the fixed value “0000001”. In Shift-IR, the shift
register portion of the instruction register forms a serial data path between TDI and
TDO. In Update-IR, the shift register contents are latched in parallel into the actual
instruction register. Note that the only time the outputs of the actual instruction
register change is during Update-IR. Therefore, a new instruction shifted into the TAP
does not take effect until the Update-IR state is visited.
TAP Instruction Register Operation
Figure 59, “TAP Instruction Register Access”
BYPASS instruction (opcode 1111111b) into the TAP instruction register. Vertical arrows
in
the Capture-IR, Shift-IR and Update-IR actions actually take place. Capture-IR (which
preloads the instruction register with 0000001b) and Shift-IR operate on rising edges
of TCK, and Update- IR (which updates the actual instruction register) takes place on
the falling edge of TCK.
Figure 59, “TAP Instruction Register Access”
illustrates the timing when loading the
show the specific clock edges on which
shows the operation of the instruction
Intel
®
5100 MCH Chipset—Testability
Order Number: 318378-005US
July 2009