HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 214

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.11
3.9.11.1
3.9.11.2
Intel
Datasheet
214
®
5100 Memory Controller Hub Chipset
Serial Presence Detect Registers
These registers appear in function 0 of different devices as shown in
“Functions Specially Handled by Intel® 5100 Memory Controller Hub Chipset.”
SPDDATA - Serial Presence Detect Status Register
This register provides the interface to the SPD bus (SCL and SDA signals) that is used
to access the Serial Presence Detect EEPROM that defines the technology,
configuration, and speed of the DIMM’s controlled by the MCH.
SPDCMD: Serial Presence Detect Command Register
A write to this register initiates a DIMM EEPROM access through the SPD bus.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:28
11:8
7:0
Bit
Bit
15
14
13
12
7:0
Bit
RWST
Attr
Attr
RO
RO
RO
RO
RO
RV
RWST
Attr
22, 21
0
144h
16
1
48h
16
1
4Ch
Default
Default
1010
00h
0h
0
0
0
0
Default
14h
RDO: Read Data Valid.
This bit is set by the MCH when the Data field of this register receives read data
from the SPD EEPROM after completion of an SPDR command. It is cleared by the
MCH when a subsequent SPDR command is issued.
WOD: Write Operation Done.
This bit is set by the MCH when a SPDW command has been completed on the SPD
bus. It is cleared by the MCH when a subsequent SPDW command is issued.
SBE: SPD Bus Error.
This bit is set by the MCH if it initiates an SPD bus transaction that does not
complete successfully. It is cleared by the MCH when an SPDR or SPDW command
is issued.
BUSY: Busy state.
This bit is set by the MCH while an SPD command is executing.
Reserved
DATA: Data.
Holds data read from SPDR commands.
DTI: Device Type Identifier.
This field specifies the device type identifier. Only devices with this device-type will
respond to commands. “1010” specifies EEPROM’s. “0110” specifies a write-protect
operation for an EEPROM. Other identifiers can be specified to target non-EEPROM
devices on the SPD bus.
DRSRENT: self-refresh entry timing - stagger of commands between
ranks
Intel
Description
Description
®
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
Table 28,
July 2009