HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 289

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.2.8.4
5.2.8.5
5.2.8.6
July 2009
Order Number: 318378-005US
Dynamic Update of Thermal Throttling Registers
In general, the Intel
during runtime as it may interfere with the internal state machines not designed
exclusively for such changes and could result in a system hang/lock up. This
requirement is relaxed (subject to validation) for the Intel
throttling registers where it is desirable for BIOS or special OEM software in BMC to
exercise dynamic control on throttling for open loop algorithm implementation. The
following examples are some of the potential areas of this usage model where dynamic
change is needed to balance performance and acoustic levels in the system.
General Software Usage Assumptions
Under normal circumstances, it is expected that there is no change of throttling values
once it is configured by BIOS during boot. The external fan control and the BIOS
settings of the OEM via BMC would ensure adequate cooling and maintain the DIMMs
within the prescribed tolerance limits of the TDP. However, situations such as thermal
virus or fan fail down condition might warrant the BIOS/software to take preemptive
action in adjusting the throttling, for example 40-70% of the normal mode, before it is
cleared. This means that changes to throttling registers can happen at random
intervals (infrequent) and the platform should be able to tolerate any transients
changes that may result when the Intel
throttle values. These requirements are captured below.
Dynamic Change Operation for Open Loop Thermal Throttling (OLTT)
The Intel
THRTHIGH (T2), THRTLOW (T1) AND GBLACT.
Each update to the above mentioned throttle register takes approximately 40 core
clocks in the configuration ring to complete.
Configuration register updates for throttling should be spaced out at approximately 80
core cycles apart. (2x guard band)
Only one CFC/CF8 or MMCFG configuration transaction is allowed at a time in the
system.
When the number of activations exceed the GBLACT.GBLACTLM in a global throttling
window, OLTT is entered and GBLTHRT is set by the Intel
consecutive global throttling windows (irrespective of the new parameters) as
described in
history-based algorithm. Hence if software assigns new values to THRTLOW or
THRHIGH values at some point in time, the Memory Controller (MC) cluster will update
the registers and use the new values for limiting the activations immediately via
THRMTHRT register for 16 consecutive global throttling windows.
Software can update the throttling registers as frequently as it desires provided it
maintains the minimum spacing for the configuration writes and follows the other
guidelines as described above. It is also software’s responsibility for the fallout/
transient effect of the thermal control algorithm during such updates.
• Fan control for CPU temperature related system acoustics or other operations
• Limit hacker activity by increasing memory throttling via throttle register updates
• Fan failure/breakdown. When this occurs, temperature conditioning can be
to condition the system based on some event (excessive bandwidth or CPU activity)
provided by reducing the activity level in the DIMMs to a certain threshold until the
failed fan can be repaired by the technician and service restored to normalcy.
®
®
5100 MCH Chipset memory throttle control register affected by OLTT include
5100 MCH Chipset
Section 5.2.8.2, “Open Loop Global
®
5100 MCH Chipset registers should not be updated dynamically
®
5100 MCH Chipset is updated with the new
Throttling”. Note that OLTT is NOT
Intel
®
®
®
5100 Memory Controller Hub Chipset
5100 MCH Chipset for 16
5100 MCH Chipset thermal
Datasheet
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