HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 383

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics—Intel
Table 130.
6.2.5
Table 131.
July 2009
Order Number: 318378-005US
Z
Z
Z
V
Notes:
1.
2.
3.
4.
5.
6.
V
V
V
I
I
C
Notes:
1.
2.
OL
Leak
RX-DIFF-DC
RX-DC
RX-HIGH-IMP-DC
RX-IDLE-DET-DIFFp
IH
IL
OL
Pad
Symbol
Symbol
A test load is not required to be associated with the values in the table.
Specified at the measurement point and measured over any 250 consecutive UIs. If the clock to the RX and TX are not
derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for
the eye diagram.
A TRX-EYE=0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected over any 250 consecutive UIs. The TRX-EYE-MEDIAN-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter
budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The
jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the
TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line
biased to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no
bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid
input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and D- line (that
is, as measured by a Vector Network Analyzer with 50 Ω probes). Note that the series capacitors CTX is optional for the
return loss measurement.
Impedance during all Link Training and Status State Machine (LTSSM) states. When transitioning from a Fundamental
Reset to Detect (the initial state of the LTSSM), there is a 5 ms transition time before receiver termination values must
be met on all un-configured lanes of a port.
The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This
helps ensure that the Receiver Detect circuit will not falsely assume a receiver is powered on when it is not. This term
must be measured at 300 mV above the RX ground.
At V
SMBus signals are OD when driving the signal. When not driving, the signals are inputs as specified.
OL
maximum, I
PCI Express*/ESI Differential Receiver (RX) Input DC Characteristics
SMBus Interfaces and Error Signals
DC Characteristics (3.3 V OD)
DC Differential Input Impedance
DC Input Impedance
Powerdown DC Input Common
Mode Impedance
Electrical Idle Detect Threshold
Input High Voltage
Input Low Voltage
Output Low Voltage
Output Low Current
Leakage Current
Pad Capacitance
OL
=maximum
®
Parameter
Parameter
5100 MCH Chipset
Min.
Min.
200
2.1
80
40
65
Nom.
Nom.
100
50
Intel
®
5100 Memory Controller Hub Chipset
Max.
Max.
120
175
0.8
0.4
60
10
10
4
Unit
Unit
mV
mA
kΩ
µA
pF
Ω
Ω
V
V
V
Datasheet
Notes
Notes
2,
5
6
1
3
383