HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 266

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 79.
4.3.6
Intel
Datasheet
266
®
5100 Memory Controller Hub Chipset
Specification, revision 1.1. Note that all subranges must be contained in the low
memory mapped I/O range (between TOLM and FE00 0000). In other words, the lowest
base address must be above TOLM and the highest LIMIT register must be below
FE00_0000. Subranges must also not overlap each other.
Low Memory Mapped I/O
The Intel
appropriate ESI or PCI Express* port. If the address is in the low MMIO range, but is
not contained in any of the PCI Express* base and limit ranges, it will be routed to the
ESI.
If the SC.PMLU and SC.PMBU registers are greater than 0, then the corresponding
prefetchable region will be located in the high MMIO range instead.
Chipset Specific Range
The address range FE00 0000h - FEBF FFFFh region is reserved for chipset specific
functions.
FE60 0000h - FE6F FFFFh: This range is used for fixed memory mapped Intel
MCH Chipset registers. They are accessible only from the processor bus. These
registers are fixed since they are needed early during the boot process. The registers
include:
These registers are described in
MCH Chipset will master abort requests to the remainder of this region unless they map
into one of the relocatable regions such as MMCFG. The mechanism for this range can
be the same as it is for the memory mapped configuration accesses.
ESI
PEX2 Memory
PEX2 Prefetchable Memory
PEX3 Memory
PEX3 Prefetchable Memory
PEX4 Memory
PEX4 Prefetchable Memory
PEX5 Memory
PEX5 Prefetchable Memory
PEX6 Memory
PEX6 Prefetchable Memory
PEX7 Memory
PEX7 Prefetchable Memory
Notes:
1.
2.
• Four Scratch Pad Registers
• Four Sticky Scratch Pad Registers
• Four Boot flag registers
• HECBASE register for MMCFG
This table assumes SC.PMLU and SC.PMBU are 0’s. Otherwise, the prefetchable memory space will be
located in high MMIO space.
MCH does not need base/limit for ICH9R because subtractive decoding will send the accesses to the
ICH9R. This is OK for software also, since the ICH9R is considered part of the same bus as the MCH.
®
I/O Port
5100 MCH Chipset will decode addresses in this range and route them to the
N/A
MBASE2
PMBASE2
MBASE3
PMBASE3
MBASE4
PMBASE4
MBASE5
PMBASE5
MBASE6
PMBASE6
MBASE7
PMBASE7
Section 3.0, “Register
2
MCH Base
Intel
1
®
5100 MCH Chipset—System Address Map
Description”. The Intel
N/A
MLIMIT2
PMLIMIT2
MLIMIT3
PMLIMIT3
MLIMIT4
PMLIMIT4
MLIMIT5
PMLIMIT5
MLIMIT6
PMLIMIT6
MLIMIT7
PMLIMIT7
2
Order Number: 318378-005US
MCH Limit
1
®
®
July 2009
5100
5100