HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 196

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.4.1
Intel
Datasheet
196
®
5100 Memory Controller Hub Chipset
DRTA[1:0]: DRAM Timing Register A
Device:
Function:
Offset:
31:27
26:21
20:15
14:7
6:2
1:0
Bit
Attr
RW
RW
RW
RW
RW
RW
22, 21
0
14Ch
Default
0Ah
0Ch
13h
10h
22h
00
T
This parameter is the smallest window over which four activations can be issued to
a given rank: no more than four activations can be issued within any given (sliding)
T
defined in mclk cycles and is set to greater than or equal to the largest T
DIMM on the memory subsystem.
Parameter depends on DRAM page size, programmed as a number of clock cycles:
Default value is Ah for 10x3.75 (266 MHz) cycles.
T
This parameter is the minimum delay from an activate command followed by a
write with page-close to another activate command on the same bank. This
parameter prevents bank activation protocol violations in the DRAM’s. This
parameter is defined in mclk cycles and is set to greater than or equal to the largest
T
(N
N
data latency, BL is the burst length, N
precharge time. Default is 4-1+8/2+4+4+4 = 19 cycles for 4-4-4 devices.
T
This parameter is the minimum delay from an activate command to another
activate or refresh command to the same bank. This parameter ensures that the
page of the bank that was opened by the first activate command is closed before
the next activate command is issued. This parameter is defined in mclk cycles and
is set to greater than or equal to the largest T
subsystem. Default is 60 ns (16 cycles) for 533 MHz devices.
T
This parameter is the minimum delay from a refresh command to another activate
or refresh command. This parameter ensures that the banks that were opened by
the refresh command are closed before the next activate command is issued. This
parameter is defined in mclk cycles and is set to greater than or equal to the largest
T
Gb 533 MHz DRAM devices.
T
This parameter is required because of page hit mode. The normal rule used to
separate activations to the same bank is T
between the activations. However, if one or more page hits occurs on the first
activate, the normal rule will not hold off the next activate for long enough. So this
rule imposes a minimum separation between a page hit read and the next activate
to the same bank. The critical case is a single page hit (T
case). T
initial activate. We subtract 4 because the conflict will be applied to the page hit
“activate” which is always 4 cycles later that the initial activate.
The equation to use to calculate this value is then the maximum of
N
N
Where N
Default value is 12 cycles for 533 MHz 4-4-4 devices.
T
This parameter specifies the average delay between two refresh commands to the
same rank over a period of nine refresh intervals (nine T
ensures that a sufficient number of refreshes per time interval are issued to each
rank. This parameter is defined in multiples of 3.9 µs. This parameter is set to less
than or equal to the smallest T
of zero disables refresh and clears the refresh counter. The default is 0 to prevent
refreshes during the init sequence. Software should program a non-zero value after
the init sequence has completed or on S3 exit. Programming a value of 3 is not
supported
FAW
WRC
RFC
FAW
WRC
RCD
RC
RFC
PHA
PHA
PHA
REF
CL
: Activate command to activate command delay (same bank)
: Refresh command to activate command delay
: Refresh command to Refresh command delay
– 1) + BL/2 + (N
of any DIMM on the memory subsystem. Default is 127.5 ns (34 cycles) for 1
: Page hit read to activate command delay (same bank)
: Electrical Throttling Window
window. This prevents DRAM power-supply droop violations. This parameter is
: Activate command to activate command delay following a DDR write
= N
= N
of any DIMM on the memory subsystem. This parameter is defined as follows:
is the DDR RAS-to-CAS delay (maximum of 5), N
RAS
RCD
RAS
RCD
(minimum) limits the earliest time the precharge can occur after the
, N
min - 4 + N
+ 2 + N
RAS
min, N
RTP
RCD
RP
RP
+ N
+ N
, and N
RP
WR
REF
Intel
+ N
RTP
of any DIMM on the memory subsystem. A value
Description
RP
®
are JEDEC supplied parameters (in cycles).
WR
) (rounded up to the nearest integer), where
5100 MCH Chipset—Register Description
is the write recovery time and N
RC
which ensures a minimum separation
RC
of any DIMM on the memory
Order Number: 318378-005US
CL
REF
RC
is the CAS-to-first-read-
s). This parameter
protects the no hit
FAW
RP
July 2009
is the
of any