HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 209

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.9.8
3.9.8.1
Table 68.
July 2009
Order Number: 318378-005US
Memory RAS Registers
There are two sets of the following registers, one set for each Memory branch. They
each appear in function 0 of different devices as shown in
Specially Handled by Intel® 5100 Memory Controller Hub Chipset.”
RANKTHRESHOLD[1:0][5:0]: RANK Count Threshold
RANKTHRESHOLD[1:0][5:0] defines the rank threshold.
There are 12 time counters, one per each rank. Each counter is cleared on reset or
when it reaches its RANKTHRESHOLD value. The output of the Error Period register is
what increments the counters. Non-zero CERRCNT counts are decremented when their
respective count register reaches the RANKTHRESHOLD values.
Characteristics of RANKTHRESHOLD”
based on the range of possible ERRPER values (0 to FFFFFFFFh).
Timing Characteristics of RANKTHRESHOLD
Device:
Function:
Offset:
Device:
Function:
Offset:
15:0
4:3
2:0
Bit
Bit
6
5
Attr
Attr
RW
RO
RO
RO
RV
®
Frequency
5100 MCH Chipset
333 MHz
266 MHz
22, 21
0
43h
22, 21
0
1BAh, 1B8h, 176h, 174h, 172h, 170h
Core
Default
000
Default
0h
0
0
0h
DSCIP: DIMM-Rank Sparing Copy In Progress
‘0’ = DIMM-rank sparing copy not in progress.
‘1’ = DIMM-rank sparing copy in progress. Set when SPCPC.SPAREN is set, and only
one rank in CERRCNT is at threshold. This bit remains set until SFO is set. This bit is
cleared when SFO is set. Error M20 is set when this bit transitions from ‘0’ to ‘1’.
SFO: Spare Fail-Over
‘0’ = Spare has not been substituted for failing rank.
‘1’ = Spare has been substituted for failing rank. Generates error M21. Cleared
when SPCPC.SPAREN is cleared.
Reserved
FR: Failed Rank
Rank that was spared. Updated with the CERRCNT rank that has reached threshold
when DSCIP is set. Read value only valid when DSCIP is set.
THRESH: CERRCNT decrement threshold.
When the counter reaches the value in this register, the leaky bucket counters
are decremented by 1.
A value of 0 prevents incrementing counter and thus decrementing CERRCNT.
Per Increment
48 ns - 206.2 s
60 ns - 257.7 s
indicates the timing characteristics of this register
Description
Description
Intel
®
(increment period x ((2^16)-1))
Table 28, “Functions
5100 Memory Controller Hub Chipset
3.15 µs - 156.4 days
Table 68, “Timing
Maximum Period
3.93 µs - 195.5 s
Datasheet
209