HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 106

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.5.2
Intel
Datasheet
106
®
5100 Memory Controller Hub Chipset
CPURSTCAPTMR: CPU Reset Done Cap Latency Timer
This register implements the cap latency method for the CPU_RST_DONE/
CPU_RST_DONE_ACK using a 12-bit variable timer.
Device:
Function:
Offset:
Device:
Function:
Offset:
12:11
15:12
7:0
Bit
Bit
15
14
13
10
9
8
RWST
RWST
ROST
Attr
Attr
RW
RW
RW
RV
RV
RV
16
0
40h
16
0
42h
Default
Default
0h
0h
0
0
0
0
0
0
0
SAVCFG: Preserve Configuration
When this bit is set, MCH configuration register contents (except for this bit)
are not cleared by hard reset. As this bit is cleared by reset, software must
set it after each reset if this behavior is desired for the next reset. If this bit
is set, BOFL will not be cleared by reset. Software should use the Boot Flag
Reset bit to re-enable the BOFL mechanism.
CPURST: Processor Reset
If set, the MCH will assert processor RESET# on both buses as soon as the
MCH has no pending transactions. The chipset will then deassert RESET#
following the timing rules described in
The MCH does not have any mechanism to drain transactions before effecting
the CPU RESET#. It is the responsibility of software to ensure that the
system is quiet before sending the configuration write (last command) to set
this field in the MCH in order to drive the CPU RESET# signal. Any violation of
this usage pattern would render the system unstable and potentially
catastrophic. This bit is self clearing.
CPUBIST: Processor Built-In-Self-Test
If set, A[3]# is asserted during Power-On-Configuration (POC), and the
processor will run BIST before engaging processor bus protocol.
Reserved
S3: S3 Sleep State
The MCH sets this bit when it sends an Ack-S3 message to the ESI port.
The MCH clears this bit after it has placed appropriate DDR channels into
self-refresh mode in response to assertion of the RESETI# signal.
ROR: Processor Reset on Refresh
If set, the MCH will assert processor RESET# on both busses when a refresh
cycle completes. This bit is self clearing.
BNR_INDP_BINIT_MODE: BNR independent of BINIT Mode
0: The chipset associates BNR with BINIT and for CPUs that do NOT follow
the “BNR independent of BINIT” feature set.
1: Enables the chipset to use the “BNR independent of BINIT” feature set,
i.e., no dependency is required between BNR and BINIT.
Refer to the BNR#, BINIT# sampling rules in the RS - Intel
Microarchitecture, Intel
HW Spec
Reserved
Reserved
®
Intel
Pentium
®
Description
Description
5100 MCH Chipset—Register Description
®
4, and Intel
Section 2.10, “Reset Requirements.”
Order Number: 318378-005US
®
Xeon
®
Processor External
®
Core™
July 2009