HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 5

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
July 2009
Order Number: 318378-005US
3.8.9
3.8.10 PCI Express* Message Signaled Interrupts (MSI) Capability Structure ......... 136
3.8.11 PCI Express* Capability Structure........................................................... 139
3.8.12 PCI Express* Advanced Error Reporting Capability .................................... 157
®
5100 MCH Chipset
3.8.8.16 MBASE[7:2] - Memory Base ..................................................... 120
3.8.8.17 MLIM[7:2]: Memory Limit ........................................................ 121
3.8.8.18 PMBASE[7:2] - Prefetchable Memory Base ................................. 121
3.8.8.19 PMLIM[7:2] - Prefetchable Memory Limit.................................... 122
3.8.8.20 PMBU[7:2] - Prefetchable Memory Base (Upper 32 Bits)............... 122
3.8.8.21 PMLU[7:2] - Prefetchable Memory Limit (Upper 32 Bits) ............... 123
3.8.8.22 IOB[7:2] - I/O Base Register (Upper 16 Bits).............................. 123
3.8.8.23 IOL[7:2] - I/O Limit Register (Upper 16 Bits).............................. 123
3.8.8.24 CAPPTR[7:2,0]- Capability Pointer............................................. 123
3.8.8.25 RBAR[7:2] - ROM Base Address Register.................................... 123
3.8.8.26 INTL[7:2,0] - Interrupt Line Register ......................................... 124
3.8.8.27 INTP[7:2,0] - Interrupt Pin Register .......................................... 124
3.8.8.28 BCTRL[7:2] - Bridge Control Register ........................................ 124
3.8.8.29 PEXLWSTPCTRL: PCI Express* Link Width Strap Control Register .. 126
3.8.8.30 CBPRES: DMA Engine Present Control Register ........................... 128
3.8.8.31 PEXCTRL[7:2,0]: PCI Express* Control Register .......................... 128
3.8.8.32 PEXCTRL2[7:2,0]: PCI Express* Control Register 2 ..................... 131
3.8.8.33 PEXCTRL3[7:2,0] - PCI Express* Control Register 3 .................... 132
3.8.8.34 PEXGCTRL - PCI Express* Global Control Register ....................... 132
3.8.8.35 INTXSWZCTRL[7:2,0]: PCI Express* Interrupt Swizzle Control Register
PCI Express* Power Management Capability Structure .............................. 134
3.8.9.1
3.8.9.2
3.8.10.1 MSICAPID[7:2,0] - MSI Capability ID ........................................ 136
3.8.10.2 MSINXPTR[7:2,0]- MSI Next Pointer.......................................... 137
3.8.10.3 MSICTRL[7:2,0] - Message Control Register ............................... 137
3.8.10.4 MSIAR[7:2,0] - MSI Address Register ........................................ 137
3.8.10.5 MSIDR[7:2,0] - MSI Data Register ............................................ 138
3.8.11.1 PEXCAPL[7:2,0]- PCI Express* Capability List Register................. 139
3.8.11.2 PEXCAP[7:2,0] - PCI Express* Capabilities Register..................... 139
3.8.11.3 PEXDEVCAP[7:2,0] - PCI Express* Device Capabilities Register ..... 140
3.8.11.4 PEXDEVCTRL[7:2,0] - PCI Express* Device Control Register ......... 141
3.8.11.5 PEXDEVSTS[7:2,0] - PCI Express* Device Status Register ............ 144
3.8.11.6 PEXLNKCAP[7:2,0] - PCI Express* Link Capabilities Register......... 144
3.8.11.7 PEXLNKCTRL[7:2,0] - PCI Express* Link Control Register ............. 146
3.8.11.8 PEXLNKSTS[7:2,0] - PCI Express* Link Status Register................ 147
3.8.11.9 PEXSLOTCAP[7:2,0] - PCI Express* Slot Capabilities Register ....... 149
3.8.11.10PEXSLOTCTRL[7:2, 0] - PCI Express* Slot Control Register .......... 150
3.8.11.11PEXSLOTSTS[7:2, 0] - PCI Express* Slot Status Register ............. 152
3.8.11.12PEXRTCTRL[7:2,0] - PCI Express* Root Control Register .............. 154
3.8.11.13PEXRTSTS[7:2,0] - PCI Express* Root Status Register ................. 155
3.8.11.14ESICTRL[0] - ESI Control Register............................................. 156
3.8.12.1 PEXENHCAP[7:2,0] - PCI Express* Enhanced Capability Header .... 157
3.8.12.2 UNCERRSTS[7:2] - Uncorrectable Error Status............................ 157
3.8.12.3 UNCERRSTS[0] - Uncorrectable Error Status For ESI Port ............. 158
3.8.12.4 UNCERRMSK[7:2] - Uncorrectable Error Mask ............................. 159
3.8.12.5 UNCERRMSK[0] - Uncorrectable Error Mask For ESI Port .............. 159
3.8.12.6 UNCERRSEV[0] - Uncorrectable Error Severity For ESI Port .......... 160
3.8.12.7 UNCERRSEV[7:2] - Uncorrectable Error Severity ......................... 161
3.8.12.8 CORERRSTS[7:2,0] - Correctable Error Status ............................ 162
3.8.12.9 CORERRMSK[7:2,0] - Correctable Error Mask ............................. 162
3.8.12.10AERRCAPCTRL[7:2,0] - Advanced Error Capabilities and Control
3.8.12.11HDRLOG0[7:2,0] - Header Log 0............................................... 163
3.8.12.12HDRLOG1[7:2,0] - Header Log 1............................................... 163
134
PMCAP[7:2,0] - Power Management Capabilities Register ............. 134
PMCSR[7:2,0] - Power Management Control and Status Register... 135
Register................................................................................. 162
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
5