HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 293

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.4.2.2
5.4.2.3
Table 93.
July 2009
Order Number: 318378-005US
The Intel
APIC ID to route interrupts. The Intel
seen on both busses and the processor with the matching APIC ID will claim the
interrupt.
Physical destination mode interrupts can be directed, broadcast, or redirected. An
XAPIC message with a destination field of all 1’s denotes a broadcast to all.
In a directed physical mode message the agent claims the interrupt if the upper eight
bits of the destination field (DID field) matches the Local APIC ID of the processor or
the interrupt is a broadcast interrupt.
Redirected interrupts are redirected and converted to a directed interrupt by the
chipset as described in
Logical Destination Mode (XAPIC)
In logical destination mode, destinations are specified using an 8-bit logical ID field.
Each processor contains a register called the Logical Destination Register (LDR) that
holds this 8-bit logical ID. Interpretation of the LDR is determined by the contents of
the processor’s Destination Format Register (DFR). Processors used with the Intel
5100 MCH Chipset operate in flat mode. Logical destination mode interrupts can be
directed (fixed delivery), redirectable (lowest priority delivery), or broadcast. The LDR
is initialized to flat mode (0) at reset and is programmed by firmware. The Intel
MCH Chipset also has an equivalent bit in the External Task Priority Register (XTPR0) to
indicate flat or cluster mode. This is set to flat mode by reset and must not be changed,
since the processors used with the Intel
The 8-bit logical ID is compared to the 8-bit destination field of the incoming interrupt
message. If there is a bit-wise match, then the local XAPIC is selected as a destination
of the interrupt. Each bit position in the destination field corresponds to an individual
Local XAPIC Unit. The flat model supports up to 8 agents in the system. An XAPIC
message where the DID (destination field) is all 1’s is a broadcast interrupt.
XAPIC Interrupt Routing
Interrupt messages that originate from I/O(x)APIC devices or from processing nodes
must be routed and delivered to the target agents in the system. In general XAPIC
messages are delivered to both processor busses because there is no reliable way to
determine the destination processor of the message from the destination field.
Interrupts originating from I/O can be generated from a PCI agent using MSI
interrupts, or by an interrupt controller on a bridge chip such as the ICH9R.
“Intel® 5100 Memory Controller Hub Chipset XAPIC Interrupt Message Routing and
Delivery”
MCH Chipset.
Message Routing and Delivery”
interrupts.
Intel
XAPIC Interrupt Message Routing and Delivery
I/O
Processor
Any Source
Source
®
5100 Memory Controller Hub Chipset
®
shows the routing rules used for routing XAPIC messages in a Intel
®
5100 MCH Chipset will not rely on the cluster ID or any other fields in the
physical or logical directed
physical or logical directed
logical, redirectable
physical, redirectable
5100 MCH Chipset
Table 93, “Intel® 5100 Memory Controller Hub Chipset XAPIC Interrupt
Type
Section 5.4.3.2, “Redirection
is valid for both broadcast and non-broadcast
Deliver to all processor busses as an interrupt transaction.
Deliver to other processor bus as an interrupt transaction.
Redirection (see
MCH Chipset and is delivered to both FSBs.
®
5100 MCH Chipset will ensure the interrupt is
®
5100 MCH Chipset operate in flat mode only.
Section
Algorithm”.
Intel
5.4.3) is performed by the Intel
®
Routing
5100 Memory Controller Hub Chipset
Table 93,
®
®
5100
®
Datasheet
5100
5100
®
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