HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 37

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 5.
July 2009
Order Number: 318378-005US
Processor Front Side Bus 0 Signals (Sheet 3 of 5)
FSB0D[63:0]#
FSB0DBI[3:0]#
FSB0DBSY#
FSB0DEFER#
FSB0DP[3:0]#
FSB0DRDY#
Signal Name
®
5100 MCH Chipset
I/O
I/O
I/O
O
I/O
I/O
Type
Processor 0 Data Bus:
FSB0D[63:0]# are the data signals. These signals provide a 64-bit data path
between the processor FSB agents. The data driver asserts FSB0DRDY# to
indicate a valid data transfer.
FSB0D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. FSB0D[63:0]# are latched off the falling edge of both
FSB0DSTBP[3:0]# and FSB0DSTBN[3:0]#. Each group of 16 data signals
correspond to one data strobe pair of FSB0DSTBP[3:0]# and
FSB0DSTBN[3:0]#. The below table shows the grouping of data signals to
strobes and FSB0DBI[3:0]#.
Furthermore, the FSB0DBI[3:0]# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one of the
FSB0DBI[3:0]# signals. When a specific FSB0DBI[3:0]# signal is active, the
corresponding data group is inverted and therefore sampled active high.
Processor 0 Dynamic Data Bus Inversion:
FSB0DBI[3:0]# are source synchronous and indicate the polarity of the
FSB0D[63:0]# signals. The FSB0DBI[3:0]# signals are activated when the data
on the data bus is inverted. If more than half the data bits, within, within a 16-
bit group, would have been asserted electronically low, the bus agent may
invert the data bus signals for that particular sub-phase for that 16-bit group.
The below table shows the signal relationships.
Processor 0 Data Bus Busy:
FSB0DBSY# is asserted by the agent responsible for driving data on the
processor FSB to indicate that the data bus is in use. The data bus is released
after FSB0DBSY# is deasserted. This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 0 Data Bus Defer:
FSB0DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Defer indicates that the MCH will terminate the
transaction currently being snooped with either a deferred response or with a
retry response.
Processor 0 Data Bus Parity:
FSB0DP[3:0]# provide parity protection for the FSB0D[63:0]# signals. They
are driven by the agent responsible for driving the FSB0D[63:0]# signals.
Processor 0 Data Ready:
FSB0DRDY# is asserted by the data driver on each data transfer, indicating
valid data on the data bus. FSB0DRDY# may be deasserted to insert idle clocks.
FSB0DRDY# is asserted for each cycle that data is transferred.
Bus Inversion Signal
FSB0D[31:16]#
FSB0D[47:32]#
FSB0D[63:48]#
FSB0D[15:0]#
Data Group
FSB0DBI[0]#
FSB0DBI[1]#
FSB0DBI[2]#
FSB0DBI[3]#
FSB0DSTB{P/N}[0]#
FSB0DSTB{P/N}[1]#
FSB0DSTB{P/N}[2]#
FSB0DSTB{P/N}[3]#
Data Strobe
FSB0D[31:16]#
FSB0D[47:32]#
FSB0D[63:48]#
FSB0D[15:0]#
Data Group
Description
Intel
®
5100 Memory Controller Hub Chipset
Bus Inversion Signal
FSB0DBI[0]#
FSB0DBI[1]#
FSB0DBI[2]#
FSB0DBI[3]#
Datasheet
37