HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 257

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.12.0.18
3.12.0.19
3.12.0.20
July 2009
Order Number: 318378-005US
BR_PMEM_LIMIT[3:2] - Bridge Prefetchable Memory Limit Register
BR_PBASE_UPPER32_P[3:2] - Bridge Prefetchable Base Upper 32
Register
BR_PLIMIT_UPPER32_P[3:2] - Bridge Prefetchable Limit Upper 32
Register
Offset:
Offset:
Offset:
15:0
31:0
31:0
Bit
Bit
Bit
Attr
Attr
Attr
RO
RO
RO
®
5100 MCH Chipset
3A6h, 326h
3A8h, 328h
3ACh, 32Ch
Default
Default
Default
0h
0h
0h
BR_PMLIM: Bridge Prefetchable Memory Limit Register
This is a copy of the Prefetchable Memory Limit Register of the virtual P2P bridge
for the PCI Express* port with which it is associated (port 3 or port 2). Refer to
Section
read, returns a value of 0h when read else return contents of BR_PMLIM field.
BR_PMBU: Bridge Prefetchable Base Upper 32 Register
This is a copy of the Prefetchable Base Upper 32 Register of the virtual P2P bridge
for the PCI Express* port with which it is associated (port 3 or port 2). Refer to
Section
when read, returns a value of 0h when read else return contents of BR_PMBU field.
Bridge Prefetchable Limit Upper 32 Register:
This is a copy of the Prefetchable Limit Upper 32 Register of the virtual P2P bridge
Section
when read, returns a value of 0h when read else return contents of BR_PMLU field.
3.8.8.19If PEXCMD.MSE=0 for the virtual P2P port, then this register when
3.8.8.20If PEXCMD.MSE==0 for the virtual P2P port, then this register
3.8.8.21If PEXCMD.MSE==0 for the virtual P2P port, then this register
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
257