HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 295

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.4.3.3
5.4.4
Note:
July 2009
Order Number: 318378-005US
XTPR Update
The Intel
redirection based on lowest priority bucket. Due to specific implementation and timing
issues in the Intel
pending interrupt (e.g., inbound MSI from PCI Express* port) happens concurrently,
the interrupt may be delivered to the prior processor thread (i.e., the CPU before
XTPR_update took effect instead of the newly redirected CPU). This is not perceived to
be a functional problem since the Intel
a valid CPU based on the XTPR register values albeit it may be older. Any subsequent
interrupts after the XTPR_update will not be affected and it will be dispatched to the
latest CPU as indicated. Although there may be negligible performance impact, the
asynchronous event may be deemed as non fatal and XTPR_updates are infrequent
that this issue is not a problem with the current implementation.
End Of Interrupt (EOI)
For XPF platforms using XAPIC, the EOI is a specially encoded processor bus
transaction with the interrupt vector attached. Since the EOI is not directed, the Intel
5100 MCH Chipset will broadcast the EOI transaction to all I/O(x)APIC’s. The
SCPEXCTRL.DIS_APIC_EOI bit per PCI Express* port can be used to determine whether
an EOI needs to be sent to a specific PCI Express* port. EOI usage is further described
in
The Intel
message type on the PCI Express*/ESI ports.
4. PHYSICAL: If Destination Mode = 0 (A[2] for I/O, FSBxAb[5]# for IPIs), then this is
5. If there are no XTPRs in the arbitration pool, then forward to FSB with A[3]=0, but
6. XTPRs in the pool are categorized into four priority buckets depending on the
7. All XTPRs in the arbitration pool are compared. The XTPR register with the lowest
8. If more than one XTPR register in the arbitration pool has the same lowest priority
9. The “winning” XTPR register provides the values to be substituted in the
Section 5.5.2, “Hardware IRQ IOxAPIC
AND XTPR[n].TPREN =1)
then XTPR[n] is included in the arbitration pool.
Physical Destination Mode. All enabled XTPRs are included in the arbitration pool.
otherwise “without modification”. Otherwise, continue to the next step.
priority. The priority bucket levels are defined by register bits BUCKET[0:2] in the
REDIRCTL register. The BUCKET fields are used to set priority group membership.
priority bucket value (0=lowest, 3=highest) is the “winner”.
bucket value, LRU arbitration logic will pick an XTPR that was not recently picked.
FSBxAa[19:12]# field of the FSB Interrupt Message Transaction driven by the
Intel
depending on the type of interrupt. The interrupt is driven onto both processor
buses with the redirection hint bit disabled (A[3]).
If (0 <= XTPR.PRIORITY < BUCKET0) then priority bucket = 0
If (BUCKET0 <= XTPR.PRIORITY < BUCKET1) then priority bucket = 1
If (BUCKET1 <= XTPR.PRIORITY < BUCKET2) then priority bucket = 2
If (BUCKET2 <= XTPR.PRIORITY < 16) then priority bucket = 3
®
®
®
®
5100 MCH Chipset. FSBxA[19:12]# is replaced by the logical or physical ID,
5100 MCH Chipset decodes FSB XTPR_Update transactions for interrupt
5100 MCH Chipset will translate the EOI on the FSB into an EOI TLP
5100 MCH Chipset
®
5100 MCH Chipset, when an XTPR_update transaction and a
®
5100 MCH Chipset will deliver the interrupt to
Interrupts”.
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
295
®