HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 134

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.35
3.8.9
3.8.9.1
Intel
Datasheet
134
®
5100 Memory Controller Hub Chipset
INTXSWZCTRL[7:2,0]: PCI Express* Interrupt Swizzle Control
Register
This register provides software the ability to swizzle the legacy interrupts (INTx) from
each port and remap them to a different interrupt type (INTA, B, C, D) for the purposes
of interrupt rebalancing to optimize system performance. This swizzling only applies to
inbound INTx messages that arrive at the various ports (including ESI). The default
setting is to have one-to-one map of the same interrupt types, i.e., (INTA => INTA,
etc.). BIOS can program this register during boot time (before enabling interrupts) to
swizzle the INTx types for the various ports within the combinations described in this
register. MCH will use the transformed INTx messages from the various ports and track
them using the bit vector as a wired-or logic for sending Assert/Deassert_INTx
messages on the ESI. For more information see
PCI Express* Power Management Capability Structure
The Intel
capabilities to handle PM events for compatibility. The PCI Express* ports can be placed
in a pseudo D3 hot state but it does have real power savings and works as if it were in
the D0 mode.
PMCAP[7:2,0] - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Device:
Function:
Offset:
7:2
1:0
Bit
RWO
®
Attr
RO
5100 MCH Chipset PCI Express* port provides basic power management
7-2,0
0
4Fh
Default
0h
00
Reserved
INTxSWZ: INTx Swizzle
The encoding below defines the target INTx type to which the incoming INTx
message is mapped to for that port. (4 combinations using the Barber-pole
slide mechanism)
00: INTA=>INTA, INTB=>INTB, INTC=>INTC, INTD=>INTD (default 1:1)
01: INTA=>INTB, INTB=>INTC, INTC=>INTD, INTD=>INTA
10: INTA=>INTC, INTB=>INTD, INTC=>INTA, INTD=>INTB
11: INTA=>INTD, INTB=>INTA, INTC=>INTB, INTD=>INTC
Intel
Section 5.10, “Interrupt Swizzling.”
®
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009