HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 387

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Testability—Intel
Figure 55.
7.1.2
July 2009
Order Number: 318378-005US
Simplified TAP Controller Block Diagram
The TAP logic consists of a finite state machine controller, a serially-accessible
instruction register, instruction decode logic and data registers. The set of data
registers includes those described in the 1149.1 standard (the bypass register, device
ID register, and so forth) plus the Intel
Accessing TAP Logic
The TAP is accessed through an 1149.1-compliant TAP controller finite state machine,
which is illustrated in
major branches represent access to either the TAP Instruction Register or to one of the
component-specific data registers. The TMS pin controls the progress through the state
machine. TAP instructions and test data are loaded serially (in the Shift-IR and Shift-DR
states, respectively) using the TDI pin. A brief description of the controller’s states
follows; refer to the IEEE 1149.1 standard for more detailed descriptions.
®
5100 MCH Chipset
Figure 55, “Simplified TAP Controller Block Diagram.”
®
5100 MCH Chipset-specific additions.
Intel
®
5100 Memory Controller Hub Chipset
The two
Datasheet
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