HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 55

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 21.
2.8
Table 22.
July 2009
Order Number: 318378-005US
Clocks, Reset and Miscellaneous Signals (Sheet 2 of 2)
Power and Ground Signals
Power and Ground Signals (Sheet 1 of 2)
PWRGOOD
PSEL[2:0]
RESETI#
RSVD
TDIOANODE
TDIOCATHODE
COREVCCA
COREVSSA
FSBVCCA
V3REF
Signal Name
Signal Name
®
5100 MCH Chipset
Core VCC (1.5 V):
Analog Voltage for the PLL
Core VSS (0 V):
Analog Voltage for PLL
FSB VCC (1.5 V):
Analog Voltage for the PLL
SMBus VCC (3.3 V):
Common Voltage for SMBus buses and other Open Drain 3.3 V referenced signals. V3REF
supplies the following signal groups: ERR[2:0]#, SMBus, RESETI#, PWRGOOD.
Connect
Analog
Analog
Type
No
I
I
I
Power Good:
PWRGOOD is an input. The MCH requires this signal to be a clean indication
that all clocks and power supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are turned
on until they come within specification. The signal must then transition
monotonically to a high state.
relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the MCH; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
Processor Speed Select:
The Processor BCLK[1:0] frequency select signals PSEL[2:0] are used to
select the processor input clock frequency. The required frequency is
determined by the processors, chipset, and clock synthesizer. All FSB agents
must operate at the same frequency. The below table indicates the currently
supported MCH FSB speeds.
For more information about these signals, including termination
recommendations, refer to the appropriate platform design guideline.
MCH Reset:
This is the hard reset
Reserved Pin:
These pins are required to be No Connects, not connected to any signal or
supply reference/voltage. The MCh may not behave as designed, if these pins
are connect to a signal or voltage level.
Thermal Diode Anode:
This is the anode of the thermal diode
Thermal Diode Cathode:
This is the cathode of the thermal diode
PSEL[2:0]
000
100
FSB Speed (MHz)
Description
Section 5.19, “System
267
333
Description
Intel
®
5100 Memory Controller Hub Chipset
Reset”describes the
Datasheet
55