HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 337

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.4.7
5.17.4.8
5.17.4.9
5.17.4.10
5.17.4.10.1 Stalled Non-Posted Requests
5.17.4.10.2 Outbound Posted Transactions
5.17.4.11
5.17.4.11.1 EOI Message
July 2009
Order Number: 318378-005US
Error Messages
PCI Express* reports many error conditions through explicit error messages:
ERR_COR, ERR_UNC, ERR_FATAL.
Inbound Vendor-Specific Messages
Assert_GPE/Deassert_GPE
Assert_GPE and Deassert_GPE form a virtual wire which is sent by a PCI Express*
device. The ICH9R component issues these messages as a response to its integrated
PCI Hot Plug* controllers.
Outbound Transactions
The MCH will generate the outbound transactions listed in
describes handling that is specific to the MCH for transactions that target a PCI
Express* interface. Ordering rules for outbound transactions are described in
Table 5.17.5.2, “Outbound Transaction Ordering
Outbound Non-Posted Transactions
Non-posted transactions that the MCH supports includes memory reads, I/O reads and
writes, and configuration reads and writes. When a non-posted transaction is issued
from the MCH, the PCI Express* device will respond with a completion.
Each PCI Express* interface supports up to four outstanding non-posted transactions
comprising transactions issued by the processors or a peer PCI Express* device.
Non-posted requests are non-blocking transactions. In other words, while a non-posted
request is pending, subsequent transactions are required to bypass the transactions
which are waiting for a completion.
Once a posted request (memory mapped I/O write) is issued from the PCI Express*
transaction layer, the request is considered to be complete and the transaction is
removed from the outbound queue. For posted requests, the acknowledge has already
been sent to the initiating interface (processor bus or alternate PCI Express* inbound
queue) when the write was enqueued in the outbound PCI Express* unit so proper
ordering is guaranteed.
Outbound Vendor-Specific Messages
The MCH supports only vendor-specific EOI messages outbound.
EOI messages will be broadcast to all the PCI Express* interfaces and require posted
transaction ordering. This ensures that the appropriate interrupt controller receives the
end-of-interrupt. Depending on outbound traffic patterns, the EOIs will often be
delivered on the PCI Express* ports at different times.
EOI is a message required for I/OAPICs which support XAPIC. Since EOI is Intel-
specific, this PCI Express* message can only be forwarded to Intel devices that support
an integrated I/OAPIC supporting level-sensitive interrupts (ICH9R).
®
5100 MCH Chipset
Rules”.
Intel
®
Table
5100 Memory Controller Hub Chipset
104. This section
Datasheet
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