HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 335

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.4.2
5.17.4.3
5.17.4.4
July 2009
Order Number: 318378-005US
Inbound Read/Write Streaming
The MCH IOU cluster implements extensive pipe-lining and non-speculative prefetching
to maximize throughput and utilization of the various PCI Express* interconnects. The
IOU uses two phases to handle a transaction. A transaction cycle starts with a
“prefetch” followed by a “fetch” cycle and terminates with a fetch completion.
In the prefetch phase, the streaming logic in the IOU breaks inbound transactions (in
the order received) into one or more cache lines and pipelines them to the CE. It should
send enough requests up to the total number of outstanding cache lines that the MCH
can handle to maximize bandwidth on the PCI Express* port. When acknowledgement
for the individual cache lines in the prefetch phase is returned, the fetch phase begins
immediately and internal commands are pipelined to the CE/DM to obtain the data as
fast as possible. Finally the data is packaged into appropriate TLPs (e.g., read
completions) and returned to the PCI Express* interface based on the request arrival
order and the appropriate completion combining conditions prevailing for that port.
Zero-Length Reads/Writes
The PCI Express* Base Specification, Rev. 1.0a describes that a zero-length memory
read must be supported and may be used by devices as a queue flushing mechanism.
With the PCI Express* ordering rules, a device can issue such a read to push ahead all
previously issued writes.
When the MCH receives a zero-length read, data is not actually read from anywhere.
Rather, the read is completed by the MCH after all writes previously posted on that
inbound port are considered to be globally visible by the system. At that point, the MCH
will return one DW of zeroes to the requesting PCI Express* port.
The PCI Express* Base Specification, Rev. 1.0a also does not preclude the arrival of
zero length writes on any of the PCI Express* ports. For coherence compatibility and
general software usage expectation, it is required to perform an RFO (Request For
Ownership) for the cache line involved in the zero length write and then commit the
unmodified cache line to memory. Similarly on the outbound path, the MCH will forward
zero length reads and writes to the respective destinations.
Inbound Write Transactions
Inbound coherent write transactions actually comprise two operations: request for
ownership, and the cache line write (mark to modified state). The PCI Express* unit will
enqueue each inbound write as a single atomic instruction. As the PCI Express* unit
enqueues the write, it will also bypass all queues by sending a request-for-ownership
command (RFO) directly to the processor buses requesting for line ownership. The RFO
commands are allowed to be issued in any order.
If the MCH owns the line after all inbound ordering rules have been met, the write
command proceeds and the line is modified. If the line is not owned by the MCH when
after all inbound ordering rules have been met, the write is temporarily stalled until
ownership is acquired and requests will continue to fill the inbound queue. When the
request for ownership completes, the write command is forwarded where the line is
marked in the modified state.
1. Prefetch Phase: The IOU launches multiple cache lines as non-speculative
2. Fetch Phase: Request data from cache lines in the CE/DM for sending to destination
prefetches for one or more enqueued requests. These prefetch commands are
routed to the Coherency Engine (CE)/Data Manager (DM) for decoding and then
sent to memory/FSB (for snoops) if required.
port. A Fetch completion is sent to terminate the cycle and remove buffer entries.
In some cases, a fetch request can be issued without a prefetch for optimization
(e.g., an initial read to memory when completion buffers are empty).
®
5100 MCH Chipset
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
335