HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 123

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.21
3.8.8.22
3.8.8.23
3.8.8.24
3.8.8.25
July 2009
Order Number: 318378-005US
If a 64-bit prefetchable memory address range is supported, the Prefetchable Base
Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers specify the upper 32-bits,
corresponding to A[63:32], of the 64-bit base and limit addresses which specify the
prefetchable memory address range.
PMLU[7:2] - Prefetchable Memory Limit (Upper 32 Bits)
IOB[7:2] - I/O Base Register (Upper 16 Bits)
Not used since MCH does not support upper 16-bit I/O addressing.
IOL[7:2] - I/O Limit Register (Upper 16 Bits)
Not used since MCH does not support upper 16-bit I/O addressing.
CAPPTR[7:2,0]- Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
this device.
It provides the offset to the first set of capabilities registers located in the PCI
compatible space from 40h. Currently the first structure is located 50h to provide room
for other registers.
RBAR[7:2] - ROM Base Address Register
Not implemented in MCH, since the MCH is a virtual PCI-to-PCI bridge.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:0
31:0
7:0
Bit
Bit
Bit
®
Attr
Attr
Attr
RW
RW
RO
5100 MCH Chipset
2-3, 4-7
0
28h
2-3, 4-7
0
2Ch
7-2, 0
0
34h
Default
Default
Default
50h
0h
0h
PUMBASE: Prefetchable Upper 32-bit Memory Base Address
Corresponds to A[63:32] of the memory address that maps to the upper base
of the prefetchable range of memory accesses that will be passed by the PCI
Express* bridge. OS should program these bits based on the available physical
limits of the system.
PUMLIM: Prefetchable Upper 32-bit Memory Limit Address
Corresponds to A[63:32] of the memory address that maps to the upper limit
of the prefetchable range of memory accesses that will be passed by the PCI
Express* bridge. OS should program these bits based on the available physical
limits of the system.
CAPPTR: Capability Pointer
Points to the first capability structure (PM) in PCI 2.3 compatible space at 50h
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
123