HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 121

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.8.17
3.8.8.18
July 2009
Order Number: 318378-005US
MLIM[7:2]: Memory Limit
This register controls the processor to PCI Express* non-prefetchable memory access
routing based on the following formula as described above:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh.
Memory range covered by MBASE and MLIM registers, are used to map non-
prefetchable PCI Express* address ranges (typically where control/status memory-
mapped I/O data structures reside) and PMBASE and PMLIM are used to map
prefetchable address ranges.
Note also that configuration software is responsible for programming all address range
registers such as MIR, MLIM, MBASE, IOLIM, IOBASE, PMBASE, PMLIM, PMBU, PMLU
(coherent, MMIO, prefetchable, non-prefetchable, I/O) with the values that provide
exclusive address ranges, i.e., prevent overlap with each other and/or with the ranges
covered with the main memory. There is no provision in the MCH hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
PMBASE[7:2] - Prefetchable Memory Base
The Prefetchable Memory Base and Memory Limit registers define a memory mapped I/
O prefetchable address range (32-bit addresses) which is used by the PCI Express*
bridge to determine when to forward memory transactions based on the following
formula:
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers
are read/write and corresponds to the upper 12 address bits, A[31:20], of 32-bit
addresses. For the purpose of address decoding, the bridge assumes that the lower 20
address bits, A[19:0], of the memory base address are zero. Similarly, the bridge
assumes that the lower 20 address bits, A[19:0], of the memory limit address (not
implemented in the Memory Limit register) are F FFFFh. Thus, the bottom of the
defined memory address range will be aligned to a 1 MB boundary and the top of the
defined memory address range will be one less than a 1 MB boundary
Device:
Function:
Offset:
15:4
3:0
Bit
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
PREFETCH_MEMORY_BASE <= A[31:20] <= PREFETCH_MEMORY_LIMIT
®
Attr
RW
RO
5100 MCH Chipset
2-3, 4-7
0
22h
Default
0h
0h
MLIMIT: Memory Limit Address
Corresponds to A[31:20] of the memory address that corresponds to the
upper limit of the range of memory accesses that will be passed by the PCI
Express* bridge
Reserved. (by PCI-SIG)
Description
Intel
®
5100 Memory Controller Hub Chipset
.
Datasheet
121