HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 110

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 51.
3.8.7
Intel
Datasheet
110
®
5100 Memory Controller Hub Chipset
these registers are modified by the xTPR_Update transaction on the processor bus.
Index into the XTPR registers is defined by
is set. This corresponds to the most significant logical thread ID or the most significant
Bus Agent ID, whichever is present.
more details on this register.
XTPR Index
These registers are used for lowest priority delivery through interrupt redirection by the
chipset. Whenever this register is updated, the “CLUSTER” bit in the register is also
updated.
PCI Express* Device Configuration Registers
This section describes the registers associated with the PCI Express* Interface.
The PCI Express* register structure is exposed to the operating system and requires a
separate device per port. Ports 2-7 will be assigned devices 2 through 7 while Port 0 is
the ESI interconnect to the ICH9R. The PCI Express* ports determine at reset the
maximum width of the devices to which they are connected through link training. All
ports will be made visible to OS even if unconnected. If Ports are combined to form
larger widths (e.g., x8 or x16 from a x4 link), then the unused ports will Master Abort
(reads return all ones, writes dropped) any accesses to it. Note that configuration
accesses to the unconnected port will still be allowed to permit device remapping, PCI
Hot Plug* etc.
Device:
Function:
Offset:
30:24
22:20
19:16
15:8
7:0
Bit
31
23
Index
3
2
1
0
if (XTPR0)
{RW}
else {RV}
endif
Attr
RW
RW
RW
RW
RV
RV
16
0
BCh, B8h, B4h, B0h, ACh, A8h, A4h, A0h, 9Ch, 98h, 94h, 90h, 8Ch, 88h, 84h, 80h
0 for FSB0, 1 for FSB1
Ab[29]
Ab[30] OR Ab[22]
Ab[21]
Default
00h
0h
0h
0h
0h
0
0
Value
CLUSTER: Global Cluster Mode (XTPR[0] only)
Used in interrupt redirection for lowest priority delivery. Updated by every
xTPR_Update transaction on either bus (Aa[3]).
Note:
Reserved
TPREN: TPR Enable
This bit reflects the value of Ab[31]#. When Ab[31]# is asserted, the value
of this bit will be 0.
Reserved
PRIORITY: Task Priority
The processor with the lowest enabled value will be assigned the
redirectable interrupt. This field is updated with Ab[27:24] of the
xTPR_Update transaction.
PHYSID: Physical APIC ID
The physical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[19:12] of the xTPR_Update transaction.
LOGID: Logical APIC ID
The logical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[11:4] of the xTPR_Update transaction.
0: flat
Cluster Mode not Supported
Section 5.4.3, “Interrupt Redirection”
Table
Intel
51. Index 1 is set if Ab[30] or Ab[22]
®
5100 MCH Chipset—Register Description
Description
Order Number: 318378-005US
describes
July 2009