HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 156

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.11.14
Intel
Datasheet
156
®
5100 Memory Controller Hub Chipset
1. PMEINTEN defined in PEXRTCTRL has to be set for PM interrupts to be generated. For non-MSI PM interrupts,
ESICTRL[0] - ESI Control Register
The ESICTRL register holds control information and defeature bits pertaining to the ESI
interface for power management.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:15
13:12
15:0
10:9
the PMESTATUS bit in each of the PEXRTSTS[2:7] registers are wired OR together and when set, the MCH will
send the “Assert_PMEGPE” message to the ICH9R for power management. When all the bits are clear, it will
send the “Deassert_PMEGPE” message. PMEINTEN defined in PEXRTCTRL has to be set for PM interrupts to be
generated. PM_PME events that generate MSI will depend on the MSIEN field in
“MSICTRL[7:2,0] - Message Control Register.”
8:4
Bit
Bit
16
14
11
RWC
RWC
Attr
Attr
RW
RW
RO
RV
RV
RV
7-2, 0
0
8Ch
0
0
D4h
Default
Default
0000h
10h
0h
0h
0
0
0
0
PMESTATUS: PME Status
This field indicates status of a PME that is underway in the PCI Express* port.
1: PME was asserted by a requester as indicated by the PMEREQID field
This bit is cleared by software by writing a ‘1’. Subsequent PMEs are kept
pending until the PME Status is cleared.
PMEREQID: PME Requester ID
This field indicates the PCI requester ID of the last PME requestor.
Reserved
DL23R: Over-ride L23 Ready - Recommend setting this bit to 1.
0: Wait for PME_Enter_L23 on all PCI Express* ports
1: Do not wait for PME_Enter_L23 on all PCI Express* ports
Reserved
PTE: PME_TO_Ack Time Expired
0: Default mode, where the SC hardware broadcasts PME_turn_off message to
all enabled PCI Express* ports.
1: Signal that time expiration has occurred when the PTOV field described
below crosses the threshold in the Intel
PTOV: PME_TO_Ack Timeout Value
00: 1 ms (default)
01: 10 ms
10: 50 ms
11: Reserved
This register field provides the timer limit for the Intel
keep track of the elapsed time from sending “PME_Turn_off” to receiving a
“PME_TO_Ack”.
Reserved
Intel
1
®
Description
Description
5100 MCH Chipset—Register Description
®
5100 MCH Chipset.
Order Number: 318378-005US
®
5100 MCH Chipset to
Section 3.8.10.3,
July 2009