HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 291

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.3
5.4
July 2009
Order Number: 318378-005US
This sequence cannot be broken in any way - once the Queue Flush is asserted, a hard
reset will be required before resuming normal operation.
Interrupts
The Intel
interrupt delivery. I/O interrupts and inter processor interrupts (IPIs) appear as write
or interrupt transactions in the system and are delivered to the target processor via the
processor bus. This chipset does not support the three-wire sideband bus (the APIC
bus) that is used by Pentium
XAPIC interrupts that are generated from I/O will need to go through an I/O(x)APIC
device unless they support Message Signaled Interrupts (MSI). In this document, I/
O(x)APIC is an interrupt controller that is found in the ICH9R component of the chipset.
The legacy 8259 functionality is embedded in the ICH9R component. The Intel
MCH Chipset will support inband 8259 interrupt messages from PCI Express* devices
for boot. The chipset also supports the processor generated “interrupt acknowledge”
(for legacy 8259 interrupts), and “end-of-interrupt” transactions (XAPIC).
Routing and delivery of interrupt messages and special transactions are described in
this section.
XAPIC Interrupt Message Delivery
The XAPIC interrupt architectures deliver interrupts to the target processor core via
interrupt messages presented on the front side bus. This section describes how
messages are routed and delivered in a Intel
description includes interrupt redirection.
Interrupts can originate from I/O(x)APIC devices or processors in the system.
Interrupts generated by I/O(x)APIC devices occur in the form of writes with a specific
address encoding. Interrupts generated by the processor appear on the processor bus
as transactions with a similar address encoding, and a specific encoding in each of the
two request phases of the FSB transaction, request phase A (REQa) and request phase
B (REQb). The values of the FSBxREQ[4:0]# signals are FSBxREQa[4:0]=01001b and
FSBxREQb[4:0]=11100b for the respective request phases. For more information, see
FSB0A[35:3]#/FSB1A[35:3]# and FSB0REQ[4:0]#/FSB1REQ[4:0]# signal
descriptions in
The naming convention throughout this section indicates ‘a’ for request phase A, ‘b’ for
request phase B and x indicates the FSB bus for which the interrupt is present. As an
example, FSBxAb[5]# refers to the FSB0/FSB1 (see
FSBxA[5]#, during the second request phase of the FSB transaction protocol, request
phase B.
The XAPIC architecture provides for lowest priority delivery, through interrupt
redirection by the chipset. If the redirectable hint bit is set in the XAPIC message, the
chipset may redirect the interrupt to another processor. Note that redirection of
interrupts can be to any processor on either Processor Bus ID and can be applied to
5. Memory Controller (MC) asserts Queues Empty when all Queues have been drained
6. MCH Power Management requests Self-refresh
7. MC initiates self-refresh command sequence on all ranks
8. MC issues Self-refresh Ack when all ranks are in self-refresh
9. Power can be removed from the MC core logic.
®
®
5100 MCH Chipset supports both the XAPIC and traditional 8259 methods of
5100 MCH Chipset
Section 2.1, “Processor Front Side Bus Signals.”
®
and Pentium
®
®
Pro processors.
5100 MCH Chipset-based system, this
Table
Intel
®
5100 Memory Controller Hub Chipset
93) address pin 5,
®
Datasheet
5100
291