HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 185
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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Register Description—Intel
3.9.1.2
3.9.1.3
July 2009
Order Number: 318378-005US
MCA - Memory Control Settings A
Additional miscellaneous control not reflected in other registers.
MS: Memory Status Register
Miscellaneous status not reflected in other registers.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:28
31:16
27:0
3:0
Bit
Bit
Bit
7
6
5
4
RWC
Attr
Attr
Attr
RW
RW
RW
RW
RV
RV
RV
®
5100 MCH Chipset
16
1
40h
16
1
58h
16
1
44h
Default
Default
DB21915h
0000h
Default
0h
0
0
0
0
2h
SCRBEN: Patrol Scrub Enable
1: Enables patrol scrubbing.
0: Disables patrol scrubbing
The scrub engine will start the scrub operations from the beginning to the end of
the memory each time the SCRBEN register bit is set.
Note that SCRBEN should be disabled during MIR updates.
DEMSEN: Demand Scrub Enable
Enables demand scrubbing.
ERRDETEN: Error Detection Enable
‘1’ = Northbound ECC checking enabled.
‘0’ = Northbound ECC checking disabled
Error logging and data poisoning are disabled when Northbound ECC checking is
disabled.
SCRBDONE: Scrub Complete
The scrub unit will set this bit to ‘1’ when it has completed scrubbing the entire
memory. Software should poll this bit after setting the Scrub Enable (SCRBEN) bit
to determine when the operation has completed. If the Scrub enable bit is cleared
midway during the scrub cycle, then the SCRBDONE bit will not be set and the
Intel
Reserved
Reserved
TO: Starvation Timeout
This timeout function is to ensure that any read request not issued within the
specified time will be given the highest priority.
A value of zero represents eight cycles. Each increment adds eight cycles.
Maximum is 128 cycles.
Reserved
®
5100 MCH Chipset will stop the scrub cycle immediately.
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
185
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