HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 249

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Offset:
13
12
11
10
9
8
7
6
5
4
Bit
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RO
RWCST
RWCST
RWCST
®
Attr
5100 MCH Chipset
228h, 1A8h, 128h, A8h
0
0
0
0
0
0
0
0
0
0
Default
int_cfg_err: Interrupt Configuration Error
The DMA channel sets this bit indicating that the interrupt registers were not
configured properly when the DMA channel attempted to generate an interrupt.
See
MSICTRL.MSIEN = 1, DMACTRL.MSICBEN = 0, PEXCMD.INTx Disable = 1
MSICTRL.MSIEN = 0, DMACTRL.MSICBEN = 1, PEXCMD.INTx Disable = 1
MSICTRL.MSIEN = 0, DMACTRL.MSICBEN = 0, PEXCMD.INTx Disable = 1
Cmp_addr_err: Completion Address Error
The DMA channel sets this bit indicating that the completion address register was
configured to an illegal address or has not been configured.
Desc_len_err: Descriptor Length Error
The DMA channel sets this bit indicating that the current transfer has an illegal
length field value. When this bit has been set, the address of the failed descriptor
and the channel returns to the Halted state, is recorded in the Channel Status
register.
Desc_ctrl_err: Descriptor Control Error
The DMA channel sets this bit indicating that the current transfer has an illegal
control field value. When this bit has been set, the address of the failed
descriptor and the channel returns to the Halted state, is recorded in the Channel
Status register.
Wr_data_err: Write Data Error
The DMA channel sets this bit indicating that the current transfer has
encountered an error while writing the destination data. When this bit has been
set, the address of the failed descriptor when the channel returns to the Halted
state, is recorded in the Channel Status register.
Rd_data_err: Read Data Error
The DMA channel sets this bit indicating that the current transfer has
encountered an error while accessing the source data. When this bit has been
set, the address of the failed descriptor when the channel returns to the Halted
state, is recorded in the Channel Status register.
DMA_data_par_err: DMA Data Parity Error
The DMA channel sets this bit indicating that the current transfer has
encountered a parity error reported by the DMA Engine. The Intel
Chipset does not implement DMA parity error detection.
Cdata_par_err: Chipset Data Parity Error
The DMA channel sets this bit indicating that the current transfer has
encountered a parity error reported by the chipset. When this bit has been set,
the address of the failed descriptor when the channel returns to the Halted state,
is recorded in the Channel Status register.
In the case of Source data (read) error, the “Rd_data_err” field is also set.
In the case of Destination (write) data error, the “Wr_data_err” field is also set
Chancmd_err: CHANCMD Error
The DMA channel sets this bit indicating that a write to the CHANCMD register
contained an invalid value (e.g., more than one command bit set). Software
should take necessary action to clear the CHANCMD register first before resetting
this register field.
Chn_addr_val_err: Chain Address Value Error
The DMA channel sets this bit indicating that the CHAINADDR register has an
illegal address including an alignment error (not on a 64-byte boundary). This
address will be checked and set by the DMA Engine during execution, i.e., when
the initial descriptor is fetched.
Section
3.11.8,
Section 3.11.1
Description
and
Intel
Section
®
5100 Memory Controller Hub Chipset
3.11.12.
®
5100 MCH
Datasheet
249