HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 168

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.22
3.8.12.23
Intel
Datasheet
168
®
5100 Memory Controller Hub Chipset
EMASK_COR_PEX[7:2,0] - Correctable Error Detect Mask
This register masks (blocks) the detection of the selected bits. Normally all are
detected. But software can choose to disable detecting any of the error bits.
EMASK_RP_PEX[7:2,0] - Root Port Error Detect Mask
This register masks (blocks) the detection of the selected bits associated with the root
port errors. Normally, all are detected.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:13
11:6
11:9
31:3
3:1
5:1
Bit
Bit
Bit
12
5
4
0
8
7
6
0
2
1
0
Attr
RW
RW
RW
Attr
RV
RV
RW
RW
RW
Attr
RV
RW
RW
RW
RW
RW
RV
RV
RV
2-3, 4-7
0
148h
7-2, 0
0
14Ch
7-2, 0
0
150h
Default
Default
Default
0h
0h
0
0
0
0h
0
0
0
0h
0h
0h
0
0
0
0
0
Reserved
IO19DetMsk: Surprise Link-down Mask
IO0DetMsk: Data Link Protocol Error Status
Reserved
IO3DetMsk:Training Error Status
This field should not be used for setting Training error severity due to a recent
PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is
undefined.
Reserved
IO1DetMsk: Fatal Message Detect Mask
IO11DetMsk: Uncorrectable Message Detect Mask
IO17DetMsk: Correctable Message Detect Mask
Reserved
IO16DetMsk: Replay Timer Timeout Mask
Reserved
IO15DetMsk: Replay_Num Rollover Mask
IO14DetMsk: Bad DLLP Mask
IO13DetMsk: Bad TLP Mask
Reserved
IO12DetMsk: Receiver Error Mask
Intel
®
Description
Description
5100 MCH Chipset—Register Description
Description
Order Number: 318378-005US
July 2009