HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 334

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 107.
5.17.3.3
5.17.4
5.17.4.1
5.17.4.1.1
Intel
Datasheet
334
Relaxed
Ordering
Snoop Not
Required
Attribute
®
5100 Memory Controller Hub Chipset
Allows the system to relax some
of the standard PCI Express*
ordering rules.
This attribute is set when an I/O
device controls coherency
through software mechanisms.
This attribute is an optimization
designed to preserve processor
bus bandwidth.
PCI Express* Attribute Handling
Traffic Class
The MCH does not support any PCI Express* virtual channels other than the default
channel (channel 0). Therefore, the MCH effectively ignores the traffic class field for
inbound requests. For inbound completions, the MCH will copy the TC value received
into the completion. For peer-to-peer completions, the TC value of the request is
preserved.
For outbound requests, the MCH sets this ID to zero.
Transaction Behavior
This section describes the specifics of how PCI Express* transactions flow through the
MCH. This section covers both generic PCI Express* transactions and ESI transactions.
Inbound Transactions
Inbound requests should be serviced to maximize PCI Express* bandwidth for the
given link without stalling. The MCH will accept the transactions listed in
section describes handling that is specific to the MCH for transactions that target the
MCH or main memory. Ordering rules for inbound transactions are described in
Section
Inbound Memory Reads
Read Completion Policy
For inbound read requests, the MCH is allowed to split completions along a Read
Completion Boundary (RCB) of 64 bytes, PEXLINKCTRL[7:2, 0]: PCI Express* Link
Control Register. For MCH, the maximum size of a read completion is specified with
Max_Payload_Size field as 256 bytes, PEXDEVCTRL[7:2, 0], PCI Express* Device
Control Register. If the PCI Express* interface is idle, the MCH will return a completion
for that read starting at the initial address up to the next cache line boundary.
If a PCI Express* interface is busy sending an outbound packet, the MCH will
opportunistically combine subsequent inbound read completions up to
Max_Payload_Size or until the initial request length is satisfied. Note that completion
combining helps increase bus efficiency due to reduced header overhead on the PCI
Express* port.
Definition
5.17.5.
For outbound
transactions, this bit
is not applicable and
set to zero.
MCH as Requester
The MCH ignores this field
on inbound transactions.
The MCH makes no
proactive attempts to
reorder differently based on
the value in this field.
If this attribute is set for
inbound transactions, the
MCH will not snoop the
transaction on the processor
buses.
Intel
MCH as Completer
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
For requests and
completions, preserve
this field from the source
PCI Express* port to the
destination port.
Peer-to-peer
Transaction
Table
106. This
July 2009