HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 12

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
12
®
5100 Memory Controller Hub Chipset
5.17
5.18
5.19
5.20
5.16.2 Using DMA ........................................................................................... 326
5.16.3 Interrupt Handling ................................................................................ 327
DMA Engine Driver........................................................................................... 329
5.17.1 Stream/Port Arbitration ......................................................................... 330
5.17.2 Supported PCI Express* Transactions ...................................................... 331
5.17.3 Transaction Descriptor........................................................................... 333
5.17.4 Transaction Behavior............................................................................. 334
5.17.5 Ordering Rules ..................................................................................... 339
5.17.6 Prefetching Policies ............................................................................... 341
5.17.7 PCI Express* Hide Bit............................................................................ 341
5.17.8 No Isochronous Support ........................................................................ 341
5.17.9 PCI Hot Plug*....................................................................................... 342
Power Management.......................................................................................... 342
5.18.1 Supported ACPI States .......................................................................... 342
System Reset.................................................................................................. 342
5.19.1 Intel
5.19.2 Intel
5.19.3 Reset Sequencing ................................................................................. 346
SMBus Interfaces Description ............................................................................ 347
5.20.1 Internal Access Mechanism .................................................................... 348
5.20.2 SMBus and PCI Express* Interoperability Timeout Recommendation ............ 348
5.20.3 SMBus Transaction Field Definitions......................................................... 349
5.16.3.1 Interrupt Service Routine (ISR) ................................................. 327
5.16.3.2 DMA Engine Interrupt Handler................................................... 328
5.16.3.3 Channel Interrupt Callback ....................................................... 328
5.17.1.1 Level 3 - IOU0, IOU1, DMA Arbitration ....................................... 330
5.17.2.1 Unsupported Messages ............................................................ 333
5.17.2.2 32/64-bit Addressing ............................................................... 333
5.17.3.1 Transaction ID ........................................................................ 333
5.17.3.2 Attributes ............................................................................... 333
5.17.3.3 Traffic Class............................................................................ 334
5.17.4.1 Inbound Transactions .............................................................. 334
5.17.4.2 Inbound Read/Write Streaming ................................................. 335
5.17.4.3 Zero-Length Reads/Writes ........................................................ 335
5.17.4.4 Inbound Write Transactions ...................................................... 335
5.17.4.5 PHOLD Support ....................................................................... 336
5.17.4.6 Interrupt Handling ................................................................... 336
5.17.4.7 Error Messages ....................................................................... 337
5.17.4.8 Inbound Vendor-Specific Messages ............................................ 337
5.17.4.9 Outbound Transactions ............................................................ 337
5.17.4.10Outbound Non-Posted Transactions ........................................... 337
5.17.4.11Outbound Vendor-Specific Messages .......................................... 337
5.17.4.12Lock Support .......................................................................... 338
5.17.4.13Peer-to-peer Transactions ........................................................ 338
5.17.4.14Peer-to-peer Configuration Cycles ............................................. 338
5.17.5.1 Inbound Transaction Ordering Rules .......................................... 339
5.17.5.2 Outbound Transaction Ordering Rules ........................................ 340
5.17.5.3 MCH Ordering Implementation .................................................. 340
5.17.5.4 Interrupt Ordering Rules .......................................................... 341
5.19.1.1 Power-Good Mechanism ........................................................... 343
5.19.1.2 Hard Reset Mechanism ............................................................. 344
5.19.1.3 Processor-Only Reset Mechanism............................................... 344
5.19.1.4 Targeted Reset Mechanism ....................................................... 344
5.19.1.5 BINIT# Mechanism .................................................................. 345
5.20.3.1 Command Field ....................................................................... 349
5.20.3.2 Byte Count Field...................................................................... 350
5.20.3.3 Address Byte 3 Field ................................................................ 350
®
®
5100 Memory Controller Hub Chipset Reset Types ........................... 343
5100 Memory Controller Hub Chipset Power Sequencing................... 345
Intel
®
5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009