HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 270

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

4.4.1
Table 81.
4.4.2
Intel
Datasheet
270
®
5100 Memory Controller Hub Chipset
Registers Used for Address Routing
Table 81, “Intel® 5100 Memory Controller Hub Chipset Memory Mapping Registers”
summary of the registers used to control memory address disposition. These registers
are described in detail in
Intel
1. The chipset treats memory and prefetchable memory the same. These are just considered 2 apertures to the
Address Disposition for Processor
The following tables define the address disposition for the Intel
Table 82, “Address Disposition for Processor”
requests entering the Intel
“Address Disposition for Inbound Transactions”
requests entering the Intel
of PCI Express*/ESI devices, please refer to the respective product specifications for
the Intel
EXSMRC, EXSMRAMC
PCI Express* port.
PMBASE (dev 2-7)
PMLIMIT (dev 2-7)
PEXCMD (dev 2-7)
MLIMIT (dev 2-7)
MBASE (dev 2-7)
PMBU (dev 2-7)
PMLU (dev 2-7)
®
EXSMRTOP
AMIR[1:0]
PAM[6:0]
HECBASE
MIR[1:0]
SMRAMC
5100 Memory Controller Hub Chipset Memory Mapping Registers
Name
BCTRL
TOLM
®
6700PXH 64-bit PCI Hub or ICH9R.
Memory Interleaving Registers (DDR2 channel interleaving)
Scratch pad register for software to use related to memory interleaving. For
example, software can write MMIO gap adjusted limits here to aid in subsequent
memory RAS operations.
Defines attributes for ranges in the C and D segments. Supports shadowing by
routing reads and writes to memory of I/O
SMM Control
Extended SMM Control
Top of extended SMM memory
Contains VGAEN and ISAEN for each PCI Express*.
Top of low memory. Everything between TOLM and 4 GB will not be sent to
memory.
Base of the memory mapped configuration region that maps to all PCI Express*
registers
Base address for memory mapped I/O to PCI Express* ports 2 - 7
Limit address for memory mapped I/O to PCI Express* ports 2 - 7
Base address for memory mapped I/O to prefetchable memory of PCI Express*
ports 2-7
Limit address for memory mapped I/O to prefetchable memory of PCI Express*
ports 2-7
Prefetchable Memory Base (Upper 32 bits) - Upper address bits to the base
address of prefetchable memory space. If the prefetchable memory is below 4 GB,
this register will be set to all 0’s.
Prefetchable Memory Limit (Upper 32 bits) - Upper address bits to the limit address
of prefetchable memory space. If the prefetchable memory is below 4 GB, this
register will be set to all 0’s.
MSE (Memory Space Enable) bit enables the memory and prefetchable ranges.
Section 3.0, “Register
®
®
5100 MCH Chipset on an I/O bus. For address dispositions
1
5100 MCH Chipset on the processor bus.
defines the disposition of outbound
Intel
defines the disposition of inbound
Description”.
®
Function
5100 MCH Chipset—System Address Map
®
Order Number: 318378-005US
5100 MCH Chipset.
Table 86,
July 2009
is a