HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 359

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Note:
5.20.6
5.20.6.1
5.20.6.2
Figure 51.
July 2009
Order Number: 318378-005US
Since the configuration registers are affected by the reset pin, SMBus masters will not
be able to access the internal registers while the system is reset.
DDR2 DIMM SPD0 SMBus Interface
The MCH integrates a 100 kHz SPD controller to access the DIMM configuration
information. SMBus There can be a maximum of eight SPD DIMMs associated with each
SPD bus. The DIMM SPD interface is wired as depicted in
DIMM Serial I/O Signals.”
Board layout must map chip selects to SPD Slave Addresses as shown in
Addressing.”
SPD Asynchronous Handshake
The SPD bus is an asynchronous serial interface. Once software issues an SPD
command (SPDCMD.CMD = SPDW or SPDR), software is responsible for verifying
command completion before another SPD command can be issued. Software can
determine the status of an SPD command by observing the SPD configuration register.
An SPD command has completed when any one command completion field (RDO, WOD,
SBE) of the SPD configuration register is observed set to 1. An SPDR command has
successfully completed when the RDO field is observed set to 1. An SPDW command
has successfully completed when the WOD field is observed set to 1. An unsuccessful
command termination is observed when the SBE field is set to 1. The MCH will clear the
SPD configuration register command completion fields automatically whenever an
SPDR or SPDW command is initiated. Polling may begin immediately after initiating an
SPD command.
Software can determine when an SPD command is being performed by observing the
BUSY field of the SPD configuration register. When this configuration bit is observed set
to 1, the interface is executing a command.
Valid SPD data is stored in the DATA field of the SPD configuration register upon
successful completion of the SPDR command (indicated by 1 in the RDO field). Data to
be written by an SPDW command is placed in the DATA field of the SPDCMD
configuration register.
Unsuccessful command termination will occur when an EEPROM does not acknowledge
a packet at any of the required ACK points, resulting in the SBE field being set to 1.
Request Packet for SPD Random Read
Upon receiving the SPDR command, the MCH generates the Random Read Register
command sequence as shown in
data is then stored in the MCH SPD configuration register in bits [7:0], and the RDO
field is set to 1 by the MCH to indicate that the data is present and that the command
has completed without error.
Random Byte Read Timing
S
T
A
R
T
D
T
3
I
D
T
2
I
Slave Address
®
D
T
1
I
5100 MCH Chipset
The slave address is written to the SPDCMD configuration register.
D
T
0
I
S
A
2
S
A
1
S
A
0
W
R
/
A
K
C
0
B
A
7
B
A
6
Byte Address
B
A
5
A
B
4
B
A
3
Figure 51, “Random Byte Read Timing.”
B
A
2
B
A
1
B
A
0
A
C
K
S
T
A
R
T
D
T
3
I
D
T
2
I
Slave Address
D
T
1
I
D
T
0
I
S
A
2
Intel
A
S
1
®
A
S
0
Figure 19, “Connection of
5100 Memory Controller Hub Chipset
R
W
/
A
K
C
1
DATA
Table 90, “SPD
The returned
N
A
K
C
Datasheet
S
T
O
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