HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 62

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.10.1.4
Figure 8.
2.10.2
Table 23.
Intel
Datasheet
62
Timing
T10
T11
T12
T13
T14
T1
T2
T3
T4
T5
T7
T8
T9
®
5100 Memory Controller Hub Chipset
Power supplies and system clocks stable to
PWRGOOD signal assertion
PWRGOOD deassertion to straps active
PWRGOOD deassertion
Power-On-Configuration (POC) after processor
RESET# assertion delay
Platform reset deassertion to platform reset
assertion
PWRGOOD assertion to POC active
PWRGOOD assertion to straps inactive
RESETI# signal assertion during PWRGOOD/
PWROK signal assertion
RESET# assertion during processor PWRGOOD
assertion
RESETI# signal deassertion to processor
RESET# signal deassertion
RESETI# signal deassertion to completion of
PCI Express* initialization sequence
Internal Memory Array Initialization duration
POC hold time after RESET# deassertion
RESETI# Retriggering Limitations
Figure 8, “RESETI# Retriggering Limitations”
RESETI# Retriggering Limitations
Reset Timing Requirements
Table 23, “Power Up and Hard Reset Timings”
“Power-Up,” Figure 6, “PWRGOOD,” Figure 7, “Hard Reset,”
Retriggering Limitations.”
hold for derated clock frequencies.
Power Up and Hard Reset Timings (Sheet 1 of 2)
RESETI#
Description
Nominal clock frequencies are described. Specifications still
2 ms
80 ns
one
BUSCLK
50
BUSCLK’s
two
BUSCLK’s
12 ns
1 ms
1 ms
480 µs
two
BUSCLK’s
Min
1
40 ns
18 ns
10 ms
1,250,000
PECLKs
200 cycles
19
BUSCLKs
Initialization
Incomplete
Max
T
shows the timing for a RESETI# retrigger.
5
specifies the timings drawn in
Intel
T
16
PLL specification. See
Figure
See
Minimum PWRGOOD deassertion time while
power and platform clocks are stable. See
Figure
See
Minimum re-trigger time on RESETI#
deassertion. See
POC turn-on delay after strap disable. See
Figure 5
This delay can be provided by the ICH or by
system logic. See
Figure 6
input.
Processor EMTS. See
Figure
Note:
See
PCI Express* clock is 100 MHz. See
Figure
CORECLK cycles. See
Figure
Processor EMTS specification.
See
Strap Hold Time. See
®
5100 MCH Chipset—Signal Description
Figure
Figure
Figure
Figure
T
9
5.
6.
7.
5,
7.
This is a special Dual-Core Intel
Xeon
requirement to have a longer POC
assertion setup time on the FSB.
and
and
and
Figure 6
6.
7.
5,
5,
Figure
Figure
®
Figure 6
Figure 6
Order Number: 318378-005US
Figure 8, “RESETI#
processor 5100 series
Complete Initialization
Comments
Figure
Figure
and
6.
7. PWROK is an ICH9R
Figure
Figure
Figure 5
Figure 4
Figure
and
and
8.
4,
Figure
Figure
Figure
5,
5,
7.
and
Figure 6
and
Figure 6
Figure 5,
7.
7.
5,
Figure
July 2009
and
and
®
6.